Digital logic for computer science

In short

Digital logic is the study of circuits that process two-valued signals: how numbers and symbols are coded in binary, how Boolean algebra describes gate networks, and how those networks are minimised and assembled into combinational and sequential blocks. Everything above it — processors, memories, controllers, network switches — is built from these blocks, so it is the foundation layer of computer science and of VLSI practice. It is a separately weighted section of GATE CS and GATE EC (typically 6–9 marks), a core second-year paper in the AICTE model curriculum ("Digital Design" / "Switching Theory and Logic Design"), and the first thing asked in VLSI and embedded interviews at Intel, Qualcomm, Nvidia, Texas Instruments, AMD, Synopsys, Cadence, Tessolve, eInfochips, Sasken, Bosch, BEL, ISRO, DRDO, C-DAC and SCL Mohali. Placement aptitude and technical rounds for product and hardware roles lean heavily on K-maps, flip-flop behaviour and timing arithmetic.

Explained

Number systems, codes and binary arithmetic

• Positional value: a number in base r is the weighted sum of its digits with weights rⁱ (integer part) and r⁻ⁱ (fraction). Bases used: binary (2), octal (8), decimal (10), hexadecimal (16).
• Conversions: decimal → base r by repeated division (integer part, read remainders upward) and repeated multiplication (fraction, read carries downward). Binary ↔ octal in groups of 3 bits, binary ↔ hex in groups of 4 bits, grouped outward from the binary point.
• Signed representations (n bits): sign-magnitude, 1's complement and 2's complement. 2's complement is universal in practice — one zero, range −2ⁿ⁻¹ to +2ⁿ⁻¹−1, and subtraction becomes addition.
• 2's complement shortcuts: invert all bits and add 1; or copy bits up to and including the rightmost 1 and invert the rest. Sign extension replicates the MSB.
• Overflow (signed): carry into the sign position ≠ carry out of it; equivalently adding two same-sign numbers gives the opposite sign. Carry out alone is not overflow in signed arithmetic — it is in unsigned.
• BCD (8421): each decimal digit in 4 bits; after adding, if a nibble exceeds 9 or produced a carry, add 6 (0110) to correct. Wastes codes (6 of 16 invalid) but eases decimal display.
• Other codes: excess-3 (BCD + 3, self-complementing), Gray code (one bit changes between successive values — used in shaft encoders, state assignment, K-map row order), ASCII (7-bit) and Unicode for characters.
• Error handling: even/odd parity detects single-bit errors; Hamming code with k check bits satisfying 2^k ≥ m + k + 1 locates and corrects one error; checksums and CRC for blocks.

Boolean algebra and logic gates

• Basic gates: AND, OR, NOT; derived NAND, NOR, XOR, XNOR. A gate's behaviour is fixed by its truth table.
• Postulates and laws: commutative, associative, distributive (both A(B+C)=AB+AC and A+BC=(A+B)(A+C)), identity (A+0=A, A·1=A), complement (A+A'=1, A·A'=0), idempotent, absorption A+AB=A, A(A+B)=A, and A+A'B=A+B.
• De Morgan's theorems: (A+B)' = A'B' and (AB)' = A'+B' — generalise to any number of variables; the basis of bubble pushing and of all-NAND/all-NOR conversion.
• Duality: swap AND↔OR and 0↔1; the dual of a valid identity is valid. The complement = dual with every literal also complemented.
• Canonical forms: SOP = sum of minterms (Σm, one term per 1-row), POS = product of maxterms (ΠM, one term per 0-row). For n variables, minterm m_i and maxterm M_i are complements; F = Σm(set) ⟺ F' = Σm(complement set) ⟺ F = ΠM(complement set).
• Universal gates: NAND and NOR each implement NOT, AND and OR, hence any function. A two-level SOP maps directly to NAND–NAND; a two-level POS maps to NOR–NOR.
• XOR facts: A⊕0=A, A⊕1=A', A⊕A=0, associative and commutative; an n-input XOR is 1 when an odd number of inputs are 1 (parity). Used in adders, comparators, parity trees, controlled inverters, LFSRs and Gray conversion.
• Counts for objective questions: there are 2²ⁿ distinct Boolean functions of n variables (16 for n = 2); a function of n variables has at most 2ⁿ minterms.
• Positive and negative logic: the same physical circuit is an AND in positive logic and an OR in negative logic — hence the duality of data sheets.

Minimisation: K-maps and Quine–McCluskey

• Why: fewer literals and terms mean fewer gates, less area, less delay and lower power — the classic exam objective is "minimum SOP/POS".
• Karnaugh map: a truth table drawn so that adjacent cells differ in one variable (Gray-coded headings). Practical up to 4–5 variables (6 with care). The map wraps around on both edges and at corners.
• Grouping rules: group 1s in powers of two (1, 2, 4, 8…); each group must be as large as possible; groups may overlap; every 1 must be covered at least once; a group of 2^k cells in an n-variable map removes k variables.
• Terminology: an implicant is any product term covering only 1s; a prime implicant cannot be enlarged; an essential prime implicant is the only one covering some minterm. Essential PIs must be in the answer; remaining 1s are covered by the cheapest selection of the rest.
• Don't cares (X / φ): input combinations that cannot occur or whose output is irrelevant (e.g. 1010–1111 in BCD). Include them to enlarge groups but never form a group of only don't cares.
• POS from a K-map: group the 0s to get the minimum SOP of F', then complement using De Morgan.
• Quine–McCluskey (tabular method): systematic and programmable — (1) list minterms in binary grouped by number of 1s; (2) combine pairs differing in one bit, marking combined terms with a dash; (3) repeat until no combination is possible; unchecked terms are prime implicants; (4) build a prime-implicant chart and choose a minimum cover (Petrick's method if needed). Handles any number of variables; grows exponentially.
• Multi-output and factored design: sharing terms between outputs, or factoring into more than two levels, can beat a per-output minimum SOP in gate count — at the cost of delay.

Combinational circuit building blocks

• Half adder: S = A⊕B, C = AB. Full adder: S = A⊕B⊕Cin, Cout = AB + Cin(A⊕B). A full adder is built from two half adders and an OR gate.
• Ripple-carry adder: n full adders chained; simple but carry propagates, so delay grows with n. Carry look-ahead computes P_i = A_i⊕B_i, G_i = A_iB_i and C_(i+1) = G_i + P_iC_i, giving nearly constant-depth carry — faster but far more gates. Carry-select and carry-save are intermediate choices.
• Subtractor: half/full subtractor (D = A⊕B⊕Bin), but in practice A − B = A + (2's complement of B), i.e. an adder with XOR inverters and Cin = 1. An adder/subtractor with a mode bit M uses B_i⊕M and Cin = M.
• Multiplexer (2ⁿ:1): n select lines choose one of 2ⁿ data inputs — a data selector, and also a function generator: any n-variable function fits a 2ⁿ:1 mux (variables on selects, constants on data), or a 2ⁿ⁻¹:1 mux with the last variable fed to data inputs.
• Demultiplexer / decoder (n:2ⁿ): activates exactly one output line. With active-high outputs, a decoder gives all minterms, so decoder + OR gates realise any set of functions; with active-low outputs, use NAND. Enable inputs allow cascading (e.g. two 74138s make a 4:16 decoder).
• Encoder (2ⁿ:n): reverse of a decoder; an ordinary encoder fails on multiple active inputs, so a priority encoder resolves by rank and provides a valid flag (used in interrupt controllers).
• Comparator: equality by XNOR of each bit pair ANDed together; magnitude comparison by examining bits from MSB downwards (A>B, A=B, A<B outputs, e.g. 7485).
• Code converters and display drivers: binary↔Gray, BCD↔excess-3, BCD-to-7-segment (7447/7448, with common-anode or common-cathode displays).
• Parity generator/checker, PLA-style arrays and ROM look-up are alternative implementations of the same truth tables; the choice is a gate-count versus memory-size trade-off.
• Lab ICs commonly used in Indian university labs: 7400 NAND, 7402 NOR, 7404 inverter, 7408 AND, 7432 OR, 7486 XOR, 7483 4-bit adder, 74138 decoder, 74151 8:1 mux, 7485 comparator.

Latches, flip-flops and sequential design

• Combinational vs sequential: a combinational output depends only on present inputs; a sequential output depends on present inputs and stored state. Sequential circuits are synchronous (clocked) or asynchronous (event-driven, harder to design).
• SR latch (NOR or NAND): level-sensitive memory; S=R=1 is forbidden in the NOR version (indeterminate). Gated/D latch adds an enable — transparent while enabled.
• Flip-flops are edge-triggered: D (Q⁺ = D), JK (Q⁺ = JQ' + K'Q, with toggle at J=K=1), T (Q⁺ = T⊕Q), and SR. Preset/clear are usually asynchronous.
• Race-around condition: in a level-triggered JK with J=K=1, the output toggles repeatedly while the clock is high if the pulse width exceeds the propagation delay. Cured by a master–slave structure or true edge triggering.
• Characteristic vs excitation tables: characteristic gives Q⁺ from inputs; excitation gives required inputs from Q→Q⁺ and is what you use in design. JK excitation: 0→0 (J=0,K=X), 0→1 (J=1,K=X), 1→0 (J=X,K=1), 1→1 (J=X,K=0).
• Flip-flop conversion: write the required Q⁺, derive the available flip-flop's inputs with a K-map (e.g. JK→D needs J = D, K = D'; D→T needs D = T⊕Q).
• Counters: asynchronous/ripple (clock of one stage from the output of the previous — simple, but delays accumulate and decoding glitches occur) and synchronous (common clock, logic generates each flip-flop's input — faster, glitch-free). Up/down, mod-N (truncated using a decode-and-clear or preset), BCD/decade, ring counter (n states, n flip-flops, one hot) and Johnson/twisted-ring counter (2n states).
• Shift registers: SISO, SIPO, PISO, PIPO and universal (74194); applications are serial–parallel conversion, delay lines, multiply/divide by 2, sequence generation and LFSR pseudo-random/CRC generation.
• Finite state machines: Moore output depends on state only (outputs appear one clock later, glitch-free); Mealy output depends on state and input (faster response, fewer states, but output follows input glitches). Design steps: state diagram → state table → state reduction/assignment → flip-flop count n = ⌈log₂(states)⌉ → excitation K-maps → next-state and output logic → verify, including the unused states.
• Registers and memory primitives: a register is a bank of flip-flops with a common clock; SRAM cells, ROM/PROM/EPROM/EEPROM/flash are the storage families (addressing and organisation are taken further in computer organisation).

Timing, hazards and practical issues

• Setup time (t_su) and hold time (t_h): the data must be stable before and after the active clock edge. Violating setup limits speed; violating hold breaks the circuit at any speed.
• Propagation delay t_cq (clock to Q) and contamination delay: the maximum path sets the clock period, the minimum path sets hold margin.
• Clock skew and jitter eat into both margins; clock trees and balanced buffers reduce skew.
• Metastability: sampling an asynchronous input near the clock edge can leave a flip-flop at an undefined level for an unbounded time; mitigated by two-flop synchronisers, handshakes and FIFOs, and quantified as MTBF — never eliminated.
• Hazards (combinational glitches): static-1 (output should stay 1 but dips), static-0 (should stay 0 but spikes), dynamic (multiple transitions on a single change). Removed by adding the redundant consensus term from the K-map (covering the adjacency between the two groups), or avoided by registering the output.
• Essential hazards afflict asynchronous sequential circuits and need delay balancing; races in asynchronous designs are critical if the final state depends on which signal wins.
• Fan-in, fan-out, loading: high fan-in slows gates; fan-out is limited by the driver's current capability and by capacitive load — buffers and tri-state drivers solve bus loading. Tri-state and open-collector/open-drain outputs (with pull-up) permit shared buses and wired-AND.
• Power: CMOS dissipation is dominated by dynamic switching power (∝ C V² f), plus short-circuit and increasingly significant leakage; clock gating, voltage scaling and lower activity reduce it.

Logic families, programmable logic and HDL

• Families: TTL (74 series: 74LS, 74S, 74ALS, 74F), CMOS (4000, 74HC/74HCT, 74AC) and ECL (fastest, high power). CMOS dominates today: negligible static power, wide supply range, high noise immunity, high input impedance; TTL is faster at older geometries and sinks more current.
• DC parameters: V_OH, V_OL, V_IH, V_IL define the noise margins; I_OL/I_IL define fan-out; interfacing families requires level checks (e.g. 74HCT is TTL-input compatible, plain 74HC is not).
• Programmable logic, in increasing flexibility: ROM/PROM (fixed AND array = full decoder, programmable OR), PAL (programmable AND, fixed OR), PLA (both programmable — most efficient in product-term sharing, slowest), CPLD and FPGA (look-up tables, flip-flops, routing, block RAM, DSP slices; configured from a bitstream). ASICs give best power/area/speed at high mask cost.
• Design flow: RTL in Verilog (IEEE 1364) / SystemVerilog (IEEE 1800) / VHDL (IEEE 1076) → simulation/testbench → synthesis → place and route → static timing analysis → bitstream or tape-out. Indian context: Xilinx/AMD and Intel FPGA boards in labs, open tool flows (Icarus Verilog, Verilator, Yosys), the India Semiconductor Mission, SCL Mohali's 180 nm fab, and indigenous RISC-V cores (IIT Madras SHAKTI, C-DAC VEGA).
• Coding discipline: use blocking assignments for combinational always blocks and non-blocking for sequential; a complete case/if-else avoids unintended latches; avoid gated and multiple clocks; keep one clock domain per module and cross domains only through synchronisers.
• Testability: scan chains, BIST, and fault models (stuck-at-0/1) make manufactured logic testable; test-pattern questions appear in VLSI interviews.

Key points

• Positional notation — digit × base^position; binary↔hex in 4-bit groups from the binary point.
• 2's complement — 2ⁿ − N; single zero, range −2ⁿ⁻¹…2ⁿ⁻¹−1, subtraction done by addition.
• Signed overflow — carry-in to the MSB ≠ carry-out of the MSB; not the same as unsigned carry.
• BCD correction — add 0110 to any nibble that exceeds 9 or generated a carry.
• Gray code — successive codes differ in one bit; g_i = b_i ⊕ b_(i+1).
• De Morgan — (AB)' = A'+B', (A+B)' = A'B'; the rule behind NAND/NOR conversion.
• NAND and NOR are universal — any function needs only one of them; SOP → NAND–NAND, POS → NOR–NOR.
• Minterm/maxterm duality — F = Σm(S) ⟺ F = ΠM(all indices not in S).
• K-map group of 2^k cells eliminates k variables; prime implicants that uniquely cover a minterm are essential.
• Don't cares enlarge groups and reduce gates, but a group of only don't cares is wrong.
• Quine–McCluskey — tabular, programmable minimisation giving all prime implicants, then a minimum cover.
• Full adder — S = A⊕B⊕Cin, Cout = AB + Cin(A⊕B); ripple carry is slow, carry look-ahead is fast and bigger.
• Mux as function generator — a 2ⁿ:1 mux realises any n-variable function; a decoder plus OR gates does the same.
• Flip-flop vs latch — flip-flops are edge-triggered; latches are level-sensitive and transparent while enabled.
• Race-around in a level-triggered JK at J=K=1, cured by master–slave or edge triggering.
• Mod-N counter needs ⌈log₂N⌉ flip-flops; ring counter n states/n flip-flops, Johnson counter 2n states.
• Mealy vs Moore — Mealy outputs change with the input (fewer states, glitch-prone); Moore outputs change only with state.
• Setup/hold and skew fix the maximum clock frequency; consensus terms remove static hazards; asynchronous inputs need synchronisers.

Formulas and examples

Example 1 — conversions, 2's complement, overflow and BCD.

• (173.625)₁₀ → binary: 173 = 10101101 (128+32+8+4+1); 0.625 = 0.101 → 10101101.101.
• Octal: group as 010 101 101 . 101 → (255.5)₈. Hex: 1010 1101 . 1010 → (AD.A)₁₆. (Check: A×16 + D = 160 + 13 = 173 ✓)
• −45 in 8-bit 2's complement: 45 = 00101101 → invert 11010010 → +1 = 11010011 = 0xD3 (= 256 − 45 = 211 unsigned ✓).
• 100 + 45 in 8-bit signed: 01100100 + 00101101 = 10010001. Carry into the sign bit is 1, carry out is 0 → overflow; the result reads as −111, because +145 does not fit in −128…+127.
• BCD 47 + 38: 0100 0111 + 0011 1000 = 0111 1111. Low nibble 1111 > 9 → add 0110: 1111 + 0110 = 1 0101, so low digit = 0101 with carry 1; high nibble 0111 + 1 = 1000. Result 1000 0101 = 85 ✓.
• Gray code of 1011: g₃ = 1, g₂ = 1⊕0 = 1, g₁ = 0⊕1 = 1, g₀ = 1⊕1 = 0 → 1110.

Example 2 — K-map with don't cares. F(A,B,C,D) = Σm(1,3,7,11,15) with don't cares d(0,2,5).

• 1s at 0001, 0011, 0111, 1011, 1111; Xs at 0000, 0010, 0101.
• Group all four cells with C = 1, D = 1 (m3, m7, m11, m15) → CD.
• Group the A = 0, B = 0 row (m0, m1, m2, m3 — two of them don't cares) → A'B'. This covers m1.
• Minimum SOP: F = CD + A'B' — 2 AND gates + 1 OR, 4 literals. Without the don't cares the answer is CD + A'B'D (5 literals), so the Xs saved one literal.
• NAND-only form: F = ((CD)' · (A'B')')' — three NAND gates plus inverters for A and B.

Example 3 — mux and decoder realisation. F(A,B,C) = Σm(1,2,4,7).

• With a 4:1 mux (A,B on selects, C as data): A'B' row has m0 = 0, m1 = 1 → I₀ = C; A'B row m2 = 1, m3 = 0 → I₁ = C'; AB' row m4 = 1, m5 = 0 → I₂ = C'; AB row m6 = 0, m7 = 1 → I₃ = C. So I₀ = C, I₁ = C', I₂ = C', I₃ = C — and the function is just A⊕B⊕C (odd parity).
• With a 3:8 decoder (active-high) plus one OR gate: F = D₁ + D₂ + D₄ + D₇. With active-low outputs, replace the OR by a NAND.
• As a ROM: 3 inputs, 1 output → 2³ × 1 = 8 bits. A BCD-to-7-segment table needs 2⁴ × 7 = 112 bits.

Example 4 — timing and maximum frequency. A synchronous block has t_cq = 1.2 ns, worst-case combinational delay 4.5 ns, t_su = 0.8 ns, clock skew 0.5 ns.

• T_clk(min) = 1.2 + 4.5 + 0.8 + 0.5 = 7.0 ns → f_max = 1/7.0 ns ≈ 142.9 MHz.
• Hold check with t_cq(min) = 0.9 ns, t_comb(min) = 0.2 ns, t_h = 0.4 ns: 0.9 + 0.2 = 1.1 ns ≥ 0.4 + 0.5 = 0.9 ns → passes.
• A 4-bit ripple counter with t_pd = 10 ns per flip-flop and 5 ns decode setup: T ≥ 4 × 10 + 5 = 45 ns → 22.2 MHz, against 1/(10 + 5) = 66.7 MHz for the synchronous version — the standard reason to prefer synchronous counters.
• 8-bit ripple-carry adder with t_g = 1.5 ns: delay ≈ (2 × 8 + 1) × 1.5 = 25.5 ns; a 4-level carry-look-ahead version ≈ 4 × 1.5 = 6 ns.
• CMOS power: α = 0.2, C = 10 pF, V = 3.3 V, f = 100 MHz → P = 0.2 × 10×10⁻¹² × 10.89 × 10⁸ ≈ 2.18 mW.

Example 5 — 3-bit synchronous up counter with T flip-flops. States 000→001→…→111→000.

• Q₀ toggles every clock → T₀ = 1. Q₁ toggles when Q₀ = 1 → T₁ = Q₀. Q₂ toggles when Q₁Q₀ = 11 → T₂ = Q₁Q₀.
• Check state 011 → 100: T₀ = 1 flips Q₀ to 0 ✓, T₁ = 1 flips Q₁ to 0 ✓, T₂ = 1 flips Q₂ to 1 ✓.
• Driven at 8 MHz, the Q₂ output is 8/2³ = 1 MHz. A mod-5 counter would need ⌈log₂5⌉ = 3 flip-flops with 3 unused states to be steered safely.

Where it is used

• VLSI and semiconductor design: RTL design, verification, synthesis and physical design roles at Intel, Qualcomm, Nvidia, AMD, Texas Instruments, Micron, Synopsys, Cadence, Siemens EDA, Tessolve, eInfochips, Sankalp and Wipro/HCL engineering, mostly in Bengaluru, Hyderabad, Noida and Pune.
• Embedded and automotive electronics: FPGA/CPLD glue logic, motor-control and sensor interfaces at Bosch, Continental, KPIT, Tata Elxsi, L&T Technology Services — including the digital logic inside BS-VI engine controllers and EV battery-management systems.
• Strategic and public-sector electronics: radar, avionics and satellite digital subsystems at ISRO, DRDO labs, BEL, HAL, ECIL and SCL Mohali, plus C-DAC's VEGA and IIT Madras' SHAKTI RISC-V cores built from the same primitives.
• Networking and data-centre hardware: switch ASICs, packet processors, SerDes and NIC logic; priority encoders and FIFOs in arbitration and scheduling.
• Instrumentation, power and railways: digital meters, protection relays, PLC and signalling logic (Indian Railways' electronic interlocking), counters and Gray-code position encoders in industrial automation.
• Exams and selection: GATE CS/EC digital logic sections, ISRO/BARC/DRDO scientist recruitment, PSU electronics papers, and the first technical round of almost every hardware or embedded placement interview.

Interview questions

• Q: Why is 2's complement preferred over sign-magnitude? A: It has a single representation of zero, a contiguous number range, and lets the same adder perform subtraction, so no separate subtractor or sign-handling logic is needed.
• Q: How do you detect signed overflow in an adder? A: XOR the carry into the MSB with the carry out of the MSB; equivalently, the sum's sign differs from both operands' signs when they are equal.
• Q: Why are NAND and NOR called universal gates? A: Each can realise NOT, AND and OR, so any Boolean function can be built using only that gate — and a two-level SOP maps directly to a NAND–NAND network.
• Q: What is the difference between a latch and a flip-flop? A: A latch is level-sensitive and transparent while enabled; a flip-flop samples only on a clock edge, which makes synchronous timing analysis possible.
• Q: What is the race-around condition and how is it removed? A: In a level-triggered JK with J=K=1, the output toggles repeatedly while the clock is high; a master–slave structure or true edge triggering limits it to one toggle per edge.
• Q: Which is better, a ripple counter or a synchronous counter? A: Synchronous — all flip-flops change together, so delay does not accumulate and the decoded outputs are glitch-free; a ripple counter is simpler and uses less logic but is slower.
• Q: What are setup and hold violations, and which is fixable by slowing the clock? A: Setup is data arriving too late before the edge and is fixed by a slower clock or shorter logic; hold is data changing too soon after the edge and is independent of clock period — it needs delay insertion or rebalancing.
• Q: What is metastability and how do you handle it? A: A flip-flop clocked while its input is changing can hover between levels for an unbounded time; two-stage synchronisers, handshakes or asynchronous FIFOs reduce the probability (raise MTBF) but cannot eliminate it.
• Q: How do you remove a static-1 hazard? A: Add the redundant consensus term that covers the adjacency between the two K-map groups being switched, or register the output so the glitch is never sampled.
• Q: Can a 4:1 multiplexer implement any 3-variable function? A: Yes — put two variables on the selects and feed each data input with 0, 1, the third variable or its complement, as read off the truth table.
• Q: How many flip-flops does a mod-12 counter need, and how many states are unused? A: ⌈log₂12⌉ = 4 flip-flops, with 4 unused states that must be steered to a valid state or made unreachable.
• Q: Compare PLA, PAL and ROM for implementing logic. A: ROM has a fixed full decoder with a programmable OR plane (wasteful for sparse functions); PAL has a programmable AND with a fixed OR (fast, cheap); PLA makes both planes programmable (best product-term sharing, slowest).
• Q: Why must unused CMOS inputs never be left floating? A: A floating high-impedance input drifts to intermediate levels, turning both transistors partly on — causing indeterminate output, oscillation and large supply current.

Common mistakes

• Grouping K-map cells in sizes that are not powers of two, forgetting the wrap-around adjacency, or forming a group entirely of don't cares.
• Confusing minterm and maxterm indexing — writing ΠM with the same index set as Σm, or complementing a POS without applying De Morgan to the whole expression.
• Treating the unsigned carry-out as signed overflow (or vice versa), and forgetting sign extension when widening a negative number.
• Skipping the BCD +6 correction, or applying it to a nibble that is ≤ 9 and produced no carry.
• Using the characteristic table instead of the excitation table when deriving flip-flop inputs in counter and FSM design, and leaving unused states unhandled so the counter can lock up.
• Ignoring hold time, clock skew and flip-flop t_cq in f_max calculations, or quoting an N-bit ripple counter's speed as if it were synchronous.
• In HDL: mixing blocking and non-blocking assignments in one always block, writing incomplete case/if statements (creating accidental latches), and feeding asynchronous inputs straight into logic without a synchroniser.

Related topics

Computer organisation and architecture · Discrete mathematics for computing · Theory of computation basics · Microprocessors and embedded systems · VLSI design and HDL (Verilog/VHDL) · Signals and digital electronics (logic families and interfacing)