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Memory management and virtual memory

Computer Science and Engineering (B.E./B.Tech) · Operating systems · free study notes for exams, placements and interviews

In short

Memory management is the part of the operating system that decides which process occupies which physical memory, translates the addresses a program uses into real RAM addresses, and protects one process's memory from another. Virtual memory extends this so a process can run with only part of its address space resident, using the disk (swap) as an extension of RAM; this is what lets a 2 GB build run on a 4 GB laptop alongside a browser. The topic is the heaviest-scoring OS area in GATE CS (address splitting, page-table size, effective access time, page-replacement traces are near-certain questions) and is standard in placement technical rounds at TCS, Infosys, Wipro, Cognizant and in system-design/debugging interviews at Amazon, Microsoft IDC, Oracle, VMware, Qualcomm and Samsung R&D. On the job it decides JVM heap sizing, container memory limits, DBMS buffer-pool tuning and why an embedded board without an MMU behaves differently.

Explained

Address binding, protection and swapping

Contiguous allocation and fragmentation

Paging

Segmentation and the x86 hybrid

Virtual memory and demand paging

Page-replacement algorithms

Frame allocation, thrashing and the working set

Key points

Formulas and examples

Logical address space = 2m bytes, page size = 2n bytes → page number p = (m − n) bits, offset d = n bits; number of pages = 2m−n
Physical address bits = log2(physical memory size) ; frame number bits = that minus n
Page-table size = 2m−n × (size of one PTE, in bytes)
EAT with TLB = h × (c + m) + (1 − h) × (c + 2m) — h = TLB hit ratio, c = TLB search time, m = one memory access (ns). Some texts take c = 0 or charge the page-table walk separately; state your convention.
EAT with demand paging = (1 − p) × ma + p × (page-fault service time) — p = page-fault rate, ma = memory access time
Average internal fragmentation per process ≈ page size / 2 ; pages needed = ceil(process size / page size)
Number of frames = physical memory size / page size
Hit ratio h = hits / total references ; fault rate = 1 − h
Thrashing condition: Σ WSS_i > m (total frames available)

1. Address splitting and page-table size. 32-bit logical addresses, 4 KB pages, 4-byte PTE, 1 GB RAM.

2. Effective access time. TLB search 20 ns, memory access 100 ns.

3. Page replacement. Reference string 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 (12 references).

Algorithm3 frames4 frames
FIFO9 faults10 faults (Belady's anomaly)
LRU10 faults8 faults
Optimal7 faults6 faults

FIFO with 3 frames, step by step: 1F[1] 2F[1,2] 3F[1,2,3] 4F evict 1→[2,3,4] 1F evict 2→[3,4,1] 2F evict 3→[4,1,2] 5F evict 4→[1,2,5] 1H 2H 3F evict 1→[2,5,3] 4F evict 2→[5,3,4] 5H = 9 faults, 3 hits. With 4 frames the same string gives 10 faults — proof that FIFO is not a stack algorithm. Optimal with 3 frames faults at references 1,2,3,4,7,10,11 = 7.

4. Fits and internal fragmentation. Holes in order: 100K, 500K, 200K, 300K, 600K. Requests in order: 212K, 417K, 112K, 426K.

Policy212K417K112K426K
First fit500K (288K left)600K (183K left)288K remnantno hole fits — must wait
Best fit300K (88K left)500K (83K left)200K (88K left)600K (174K left) — all fit
Worst fit600K (388K left)500K (83K left)388K remnantno hole fits — must wait

5. Segmentation translation and thrashing. Segment table: s0 base 1400 limit 1000; s1 base 6300 limit 400; s2 base 4300 limit 400; s3 base 3200 limit 1100.

Where it is used

Interview questions

Common mistakes

Related topics

Processes and threads · CPU scheduling · File systems and disk scheduling · I/O systems and device management · Virtualisation and containers · Cache memory and memory hierarchy (Computer Organisation)

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