Logic families and semiconductor memories

Electronics and Communication Engineering (B.E./B.Tech) · Digital electronics · free study notes for exams, placements and interviews

In short

A logic family is a set of ICs built on one circuit technology (bipolar TTL/ECL, or MOS/CMOS) so that their voltage levels, drive currents, speeds and power figures are mutually compatible. Semiconductor memories are regular arrays of those same transistors used to store bits — volatile RAM (SRAM, DRAM) and non-volatile ROM/flash. Together they decide whether a digital design actually works at speed: noise margins and fan-out govern interfacing, and memory access time plus refresh govern system timing. The topic is heavily examined in GATE EC/EE/IN, ISRO, BARC and DRDO papers, and in placement rounds at Micron, Samsung Semiconductor India, Intel, Qualcomm, Texas Instruments, Synopsys, Cadence, BEL, SCL Mohali and VLSI service firms such as Tessolve and Sankalp.

Explained

Characteristic parameters of a logic family

Logic levels: VOH(min), VOL(max) are what an output guarantees; VIH(min), VIL(max) are what an input accepts. The band between VIL and VIH is the forbidden/indeterminate region.
Noise margin: ΔH = VOH(min) − VIH(min), ΔL = VIL(max) − VOL(max). The family's noise immunity is the smaller of the two.
Fan-in: number of inputs a gate has. Fan-out: number of same-family inputs one output can drive, limited by current sourcing/sinking, not voltage.
Propagation delay: tPLH and tPHL; tpd is usually quoted as their average. Power dissipation Pd per gate (quiescent for bipolar, mostly dynamic for CMOS).
Speed-power product = tpd × Pd, in picojoules — the figure of merit for comparing families (lower is better).
Others: supply range, operating temperature (commercial 0–70 °C, industrial −40–85 °C, military −55–125 °C), current transients, and cost.

Bipolar families: TTL and ECL

Evolution: RTL → DTL → TTL (transistor-transistor logic) → ECL. RTL/DTL are obsolete but asked for their poor fan-out and speed.
Standard TTL NAND (7400): a multi-emitter input transistor performs the AND, a phase-splitter transistor drives a totem-pole output (pull-up transistor + diode above, pull-down transistor below). The output stage gives low output impedance in both states, hence good drive and speed, but produces current spikes when both transistors conduct momentarily — hence the need for supply decoupling capacitors.
Saturated logic: transistors go into saturation, and storage time limits speed. Schottky clamping (74S, 74LS, 74AS, 74ALS, 74F) prevents saturation and cuts delay.
TTL sub-families: 74 (standard), 74L (low power, slow), 74H (fast, power hungry), 74LS (the classic lab workhorse), 74S, 74ALS, 74AS, 74F.
Open-collector output: pull-down transistor only; needs an external pull-up resistor. Outputs may be tied together to give wired-AND (active-low bus, I²C, interrupt lines, lamp drivers). Slower rise time (RC limited).
Tri-state (three-state) output: totem-pole plus an enable; the third state is high-impedance, so many drivers can share a bus with only one enabled. Used in all memory data buses.
TTL input quirks: a floating TTL input behaves as logic 1 (but is noise-prone); unused inputs should be tied to VCC through 1 kΩ or to a used input.
ECL (emitter-coupled logic): a differential amplifier pair operating in the active region, never saturated, with emitter-follower outputs; typically VEE = −5.2 V, VOH ≈ −0.9 V, VOL ≈ −1.75 V. Fastest family (sub-nanosecond), has complementary outputs and allows wired-OR, but draws large constant current and has a small noise margin (~0.2 V). Used in ATE, high-speed instrumentation, old supercomputers; today largely replaced by LVDS/CML.
I²L (integrated injection logic): very high packing density, low speed — historical, LSI only.

MOS and CMOS families

CMOS inverter: series PMOS (pull-up) and NMOS (pull-down) with gates tied together. Only one conducts in steady state, so static current is leakage only; the switching threshold is near VDD/2 for a matched pair.
CMOS gate construction: NAND = series NMOS + parallel PMOS; NOR = parallel NMOS + series PMOS. An n-input CMOS gate needs 2n transistors.
Advantages: near-zero static power, rail-to-rail swing, wide noise margin (≈0.3 VDD typical), very high input impedance so fan-out is limited by capacitance and hence speed, not by DC current; symmetric and scalable.
Limitations: power rises with frequency; sensitive to ESD (handling precautions, antistatic bags, grounded wrist straps); latch-up — a parasitic p-n-p-n SCR latches a short between VDD and ground, prevented by guard rings, substrate taps and epitaxial substrates; unused CMOS inputs must never be left floating (they oscillate and draw large current).
Sub-families: 4000B/74C (3–18 V, slow), 74HC (high-speed CMOS, CMOS input thresholds), 74HCT (TTL-compatible thresholds, for TTL-to-CMOS interfacing), 74AC/ACT, and low-voltage 74LVC/ALVC/LVX at 3.3 V, 2.5 V, 1.8 V.
Transmission gate / pass transistor: NMOS + PMOS in parallel acting as a bidirectional analogue-digital switch; the basis of multiplexers, latches and the 4016/4066 switch ICs.
BiCMOS: CMOS logic core with bipolar output drivers — CMOS density with bipolar drive, used in bus interface and mixed-signal parts.
Interfacing rules: TTL output (VOH min 2.7 V) cannot reliably drive a 74HC input (VIH 3.15 V at VCC = 4.5 V) → use 74HCT, or a pull-up resistor. A 4000-series output has weak drive → use a 4049/4050 buffer to drive TTL. Different supplies need level shifters or open-drain plus pull-up to the lower rail.

Semiconductor memory: classification and organisation

Volatile: SRAM (bistable latch per cell, no refresh, fast, 6 transistors, low density, expensive) and DRAM (one transistor + one capacitor, must be refreshed, high density, cheap per bit).
Non-volatile: mask ROM (programmed at fabrication, cheapest in volume), PROM (fusible links, one-time), EPROM (floating gate, UV erase through a quartz window, bulk erase), EEPROM/E²PROM (electrically erasable byte-wise, used for calibration and configuration), flash (electrically erasable in blocks).
Flash types: NOR flash — random byte read, used for boot code and firmware; NAND flash — page read/program, block erase, far denser, used in SSDs, eMMC, UFS and pen drives. Endurance roughly 10⁵ cycles for SLC down to ~10³ for QLC; needs wear levelling, bad-block management and ECC. 3D (vertical) NAND stacks hundreds of layers.
Emerging NVM: FRAM, MRAM/STT-MRAM, PCM and ReRAM — byte-alterable, fast, high endurance; used in microcontrollers and as storage-class memory.
Organisation: a memory of 2ⁿ words × m bits has n address lines, m data lines, plus CS/CE (chip select), OE/RD and WE/WR. The array is a square-ish matrix with a row decoder and a column decoder/MUX.
Static RAM cell (6T): two cross-coupled inverters holding the bit, two access NMOS transistors connecting it to bit-line and bit-line-bar, gated by the word line. Read and write via the differential bit lines with a sense amplifier.
Dynamic RAM cell (1T1C): charge on a small capacitor; reading is destructive (charge is shared with the bit line) so every read is followed by a write-back. Addressing is split into RAS (row address strobe) and CAS (column address strobe) to halve the pin count.
Refresh: leakage drains the cell, so every row must be rewritten within the retention/refresh period (classically 64 ms, often 32 ms above 85 °C — exact values are JEDEC device parameters, check the datasheet). Burst refresh does all rows together; distributed refresh spaces them evenly (interval tREFI); self-refresh uses an on-chip timer in low-power modes.
DRAM generations: asynchronous (FPM, EDO) → SDRAM (clocked, banked, burst) → DDR, DDR2, DDR3, DDR4, DDR5 (both clock edges, 2ⁿ prefetch, on-die termination); mobile LPDDR, graphics GDDR, and stacked HBM. Timing is quoted as CL-tRCD-tRP-tRAS in clock cycles.
Special memories: content-addressable memory (CAM) searches by data and returns the address (routers, TLBs); FIFO for rate matching; dual-port RAM for two simultaneous accesses; register file inside a CPU.

Memory expansion, decoding and timing

Word (vertical) expansion increases the number of locations: data lines are paralleled, extra high-order address lines drive a decoder that selects one chip via CS.
Bit (horizontal) expansion increases word width: the same address and CS go to all chips, data lines are concatenated.
Both together: chips needed = (required capacity in bits) ÷ (chip capacity in bits), arranged in rows × columns.
Absolute decoding uses every unused address line (a unique address per location, no aliasing); partial/linear decoding leaves lines unused (cheap, but creates foldback — a chip responds at several addresses).
Timing parameters: access time tAA (address to valid data), tCO (chip-select to output), read cycle time tRC, write pulse width tWP, data setup/hold around WE, output-enable access time tOE. Wait states are inserted when memory is slower than the processor's bus cycle.
Memory hierarchy: registers → L1/L2/L3 SRAM cache → DRAM main memory → flash/SSD → disk/tape; cost per bit falls and access time rises down the chain. Locality of reference is what makes it work.
ROM as a logic element: a 2ⁿ × m ROM is a complete lookup table implementing any m Boolean functions of n variables — the canonical "ROM realises a truth table directly" result.

Comparison and selection in practice

Speed order (fastest first): ECL → 74AS/F → 74AC → 74S → 74ALS → 74HC ≈ 74LS → 74 → 4000B.
Power order (lowest static first): CMOS (static ≈ nW) → 74ALS/LS → 74 → 74S → ECL.
For battery and portable work: low-voltage CMOS. For maximum speed with no power constraint: ECL/CML. For glue logic on a 5 V board: 74LS or 74HCT. Today most random logic is absorbed into FPGAs/ASICs, and discrete families survive mainly as level translators, buffers and bus interfaces.
Indian practice and standards: device parameters follow JEDEC (JESD) standards; BIS/IS adopts IEC safety and EMC standards for the end products; SCL Mohali (Department of Space) runs an indigenous 180 nm CMOS line for strategic ICs. Under the India Semiconductor Mission (2021), Micron's assembly-and-test plant at Sanand (Gujarat) packages DRAM/NAND and the Tata–PSMC fab at Dholera is under construction — figures and timelines in this sector change fast, so verify current status before quoting it.

Key points

Logic family - one circuit technology giving mutually compatible levels, drive and speed.
Noise margin - the smaller of (VOH−VIH) and (VIL−VOL); CMOS ≈ 1.25 V at 5 V, 74LS ≈ 0.3 V, ECL ≈ 0.2 V.
Fan-out - minimum of IOL/IIL and IOH/IIH; 10 for standard TTL, 20 for 74LS, effectively capacitance-limited in CMOS.
Totem-pole output - low impedance both states; must never be tied in parallel.
Open collector - needs a pull-up; parallel outputs give wired-AND; ECL gives wired-OR.
Tri-state - third high-impedance state; the standard way to share a data bus.
Schottky clamp - keeps the transistor out of saturation, removing storage time delay.
ECL - non-saturating differential logic, fastest, negative supply, high constant power.
CMOS dynamic power - P = α·CL·VDD²·f; halving the supply cuts power ~4×.
Latch-up - parasitic SCR short in CMOS; prevented by guard rings and substrate contacts.
Floating inputs - read as 1 in TTL, cause oscillation and heavy current in CMOS; always tie them.
SRAM - 6T latch cell, no refresh, 1–10 ns, used for cache and scratchpad.
DRAM - 1T1C cell, destructive read, needs refresh (classically every 64 ms per row), densest volatile memory.
RAS/CAS - row/column address multiplexing to cut DRAM pin count.
NOR vs NAND flash - NOR for random-read code, NAND for dense block storage.
2ⁿ × m memory - n address pins, m data pins; capacity in bits = 2ⁿ × m.
Absolute vs partial decoding - unique address versus cheap decoding with address foldback.
ROM as logic - a 2ⁿ × m ROM implements any m functions of n variables as a truth table.

Formulas and examples

Noise margin: ΔH = VOH(min) − VIH(min); ΔL = VIL(max) − VOL(max); NM = min(ΔH, ΔL) [volts]
Fan-out N = min[ IOL(max)/IIL(max) , IOH(max)/IIH(max) ] (currents in mA or µA, same unit both sides)
Propagation delay tpd = (tPLH + tPHL)/2 [ns]; Speed–power product = tpd × Pd [pJ = ns × mW]
CMOS dynamic power Pd = α·CL·VDD²·f (α = activity factor, CL in farads, VDD in volts, f in hertz, P in watts)
CMOS short-circuit + leakage: Ptotal = α·CL·VDD²·f + Isc·VDD + Ileak·VDD
Open-collector pull-up: Rp(min) = [VCC − VOL(max)] / [IOL(max) − N·IIL]; Rp(max) = [VCC − VIH(min)] / [n·IIH + m·ICEX]
Memory capacity (bits) = 2ⁿ × m; address lines n = log₂(number of words)
Chips required = (required capacity in bits) / (one chip's capacity in bits); rows = words ratio, columns = width ratio
DRAM distributed refresh interval tREFI = (refresh period) / (number of rows)
Refresh overhead = (rows × row-refresh time) / refresh period × 100 %
Wait states = ceil(memory access time / clock period) − 1
Effective access time (two levels) = h·tcache + (1 − h)·tmiss, h = hit ratio
Bus bandwidth = (bus width in bytes) × (transfers per second)

1. Noise margin and fan-out of 74LS versus 74HC. 74LS: VOH(min) = 2.7 V, VIH(min) = 2.0 V → ΔH = 0.7 V; VIL(max) = 0.8 V, VOL(max) = 0.5 V → ΔL = 0.3 V → NM = 0.3 V. Fan-out: IOL = 8 mA, IIL = 0.4 mA → 20; IOH = 400 µA, IIH = 20 µA → 20 → fan-out = 20. 74HC at VCC = 4.5 V: VOH = 4.4 V, VIH = 3.15 V → ΔH = 1.25 V; VIL = 1.35 V, VOL = 0.1 V → ΔL = 1.25 V → NM = 1.25 V, about four times better.

2. CMOS power versus supply and frequency. CL = 20 pF, α = 1, f = 10 MHz. At 5 V: P = 20×10⁻¹² × 25 × 10×10⁶ = 5 mW. At 3.3 V: P = 20×10⁻¹² × 10.89 × 10×10⁶ = 2.18 mW — a 56 % saving for a 34 % voltage cut. At 1 kHz the same gate dissipates 0.5 µW, which is why CMOS is called "power on demand".

3. Open-collector pull-up resistor. VCC = 5 V, output sinks IOL = 16 mA at VOL = 0.4 V, driving 4 TTL inputs (IIL = 1.6 mA each, IIH = 40 µA each), with 4 open-collector outputs tied together (leakage ICEX = 250 µA each). Rp(min) = (5 − 0.4)/(16 − 4×1.6) mA = 4.6/9.6 mA ≈ 479 Ω. Rp(max) = (5 − 2.0)/(4×40 µA + 4×250 µA) = 3/1.16 mA ≈ 2.59 kΩ. Choose a standard 1 kΩ; a lower value gives faster rise time, a higher value less current.

4. Memory expansion: build 16K × 8 from 4K × 4 chips. Capacity needed = 16384 × 8 = 131072 bits; one chip = 4096 × 4 = 16384 bits → 8 chips. Arrangement: 16K/4K = 4 rows (word expansion) × 8/4 = 2 columns (bit expansion). Pins: the chip has log₂4096 = 12 address lines and 4 data lines. The system needs log₂16384 = 14 address lines, so A0–A11 go to all chips and A12–A13 drive a 2-to-4 decoder whose outputs are the four row chip-selects. If the block starts at 0000H: chips select 0000–0FFFH, 1000–1FFFH, 2000–2FFFH, 3000–3FFFH.

5. DRAM refresh arithmetic. A DRAM with 8192 rows and a 64 ms refresh period. Distributed interval tREFI = 64 ms / 8192 = 7.8125 µs — one row every 7.81 µs. If one row refresh occupies 60 ns, overhead = 8192 × 60 ns = 491.5 µs in 64 ms = 0.77 % of the time. At 95 °C the retention period halves to 32 ms, so tREFI becomes 3.91 µs and overhead doubles to 1.54 %.

6. Wait states and effective access time. A 100 MHz processor (10 ns clock) with 60 ns DRAM: cycles = ceil(60/10) = 6, so 5 wait states. Add a 10 ns SRAM cache with 95 % hit ratio, miss costing 10 + 60 = 70 ns: effective time = 0.95×10 + 0.05×70 = 9.5 + 3.5 = 13 ns — close to SRAM speed at DRAM cost. A 64-bit DDR4-3200 bus gives 3200 MT/s × 8 bytes = 25.6 GB/s.

Family	tpd (ns)	Pd/gate (mW)	Speed–power (pJ)	Fan-out	Noise margin
74 (TTL)	10	10	100	10	0.4 V
74LS	9.5	2	~19	20	0.3 V
74S	3	19	~57	20	0.3 V
74AS	1.7	8	~14	40	0.3 V
74ALS	4	1.2	~4.8	20	0.3 V
ECL 10K	2	25	~50	25	~0.2 V
4000B (5 V)	50	~0.001 static	very low	>50	~1.5 V
74HC (5 V)	8	~0.001 static	very low	>50	1.25 V

Feature	SRAM	DRAM	NOR flash	NAND flash
Cell	6 transistors	1T + 1C	1 floating-gate T	1 floating-gate T (series string)
Volatile	Yes	Yes (needs refresh)	No	No
Access	1–10 ns	20–60 ns (array)	50–100 ns read	µs page read
Write/erase	Same as read	Same as read	Slow, sector erase	Page program, block erase
Density/cost	Low / high	High / low	Medium	Highest / lowest
Typical use	Cache, FPGA, registers	Main memory	Boot code, firmware	SSD, eMMC, UFS, cards

Where it is used

Memory fabrication, assembly and test: Micron's ATMP plant at Sanand packages and tests DRAM and NAND; process, product and test engineering roles in Gujarat and at design centres in Hyderabad and Bengaluru.
VLSI design and verification: standard-cell library characterisation (tpd, power, noise), memory compilers, SRAM/DRAM design and DFT/BIST at Intel, Samsung, Qualcomm, TI, Synopsys and Cadence India; March-algorithm memory BIST is a staple interview topic.
Embedded and board design: choosing 74HCT/LVC level translators, I²C open-drain buses with pull-ups, DDR routing and termination, eMMC/NOR boot memory selection in automotive ECUs, smart meters and set-top boxes.
Strategic and space electronics: SCL Mohali's 180 nm CMOS line, radiation-tolerant SRAM/EEPROM and latch-up-immune design for ISRO payloads; BEL and DRDO radar and avionics hardware.
Test and validation services: Tessolve, Sankalp, SmartSoC and similar firms doing ATE program development, memory characterisation, shmoo plots and reliability/endurance qualification.
Exams and recruitment tests: GATE EC/EE/IN numericals on noise margin, fan-out, decoding and refresh; ISRO, BARC, DRDO, BSNL JTO, PSU and campus written rounds.

Interview questions

Q: Why can two totem-pole TTL outputs not be connected together? A: If one drives high and the other low, a low-impedance path forms from VCC to ground through both output stages, giving an indeterminate level and possible device damage; use open-collector or tri-state outputs instead.
Q: What is the difference between open-collector and tri-state outputs? A: Open collector pulls low or floats and needs an external pull-up (giving wired-AND); a tri-state output can actively drive high, drive low, or go high-impedance under an enable, and so is faster on buses.
Q: Why is ECL faster than TTL? A: Its transistors operate in the active region and never saturate, so there is no storage-time delay, and the signal swing is small (~0.8 V), which charges load capacitances quickly.
Q: How is fan-out calculated, and why is it so large for CMOS? A: Fan-out is the lesser of IOL/IIL and IOH/IIH; CMOS gate inputs draw only leakage current (nanoamperes), so the DC fan-out is huge and the real limit is the added capacitance slowing switching.
Q: What happens if a CMOS input is left floating? A: It can drift into the transition region, turning both transistors partly on, which causes oscillation, excessive supply current and heating — unused inputs must be tied to VDD or ground.
Q: What is latch-up and how is it prevented? A: A parasitic p-n-p-n structure between well and substrate turns on as an SCR and shorts the supply; prevention uses guard rings, plenty of well and substrate contacts, epitaxial or SOI substrates, and input clamping.
Q: Can a 74LS output directly drive a 74HC input? A: Not reliably — 74LS guarantees only 2.7 V high while 74HC needs about 3.15 V; use a 74HCT part (TTL thresholds) or a pull-up resistor to VCC.
Q: Why does a DRAM read need a write-back? A: Reading shares the cell capacitor's charge with the bit line and destroys the stored level, so the sense amplifier must restore it to the cell after sensing.
Q: Why does DRAM use multiplexed RAS/CAS addressing? A: Sending the row and column halves of the address on the same pins at different times halves the number of address pins, which matters greatly in a high-density, cost-sensitive part.
Q: Compare SRAM and DRAM for a cache. A: SRAM is chosen because it is several times faster, needs no refresh and has deterministic access; its six-transistor cell costs area, which is acceptable for the small capacity a cache needs.
Q: Why is NAND flash used in SSDs rather than NOR? A: NAND's series-string cell is far denser and cheaper per bit and supports fast page programming and block erase, which suits bulk storage; NOR's random-byte read suits code execution instead.
Q: How many chips and address lines are needed to build 32K × 16 memory from 8K × 8 chips? A: 32K/8K = 4 rows × 16/8 = 2 columns = 8 chips; the system needs 15 address lines, with A0–A12 to the chips and A13–A14 into a 2-to-4 decoder for the chip selects.

Common mistakes

Taking the noise margin as the larger of ΔH and ΔL, or forgetting to use worst-case (min/max) datasheet values rather than typical ones.
Mixing the two current pairs when finding fan-out — IOL must be divided by IIL, and IOH by IIH, and the smaller result taken.
Treating CMOS fan-out as unlimited and ignoring the propagation delay added by load capacitance.
Forgetting the pull-up resistor on open-collector or I²C lines, or sizing it from only one of the two limits.
Confusing wired-AND (open-collector TTL) with wired-OR (ECL), and assuming any two outputs may be paralleled.
Computing memory chip counts in words instead of bits, or assigning the low-order address lines to the decoder instead of the high-order ones.
Quoting a DRAM refresh interval per chip when the specification is per row, and ignoring that retention time halves at high temperature.
Calling EEPROM and flash the same thing — flash erases only in blocks, EEPROM is byte-alterable.