MOS device physics: scaling and short-channel effects

In short

Scaling means shrinking a MOSFET's channel length, oxide thickness and supply voltage together so that more, faster, cheaper transistors fit on a die — the engine behind Moore's law. Below roughly 1 µm the gate stops being the only controller of the channel: the drain field reaches into it, carriers hit their velocity limit, and leakage and reliability problems appear. These deviations from long-channel theory are the short-channel effects (SCE), and the device-level fixes (LDD, halo doping, thin oxide, high-k metal gate, SOI, FinFET, GAA) are what this topic covers. It is a heavily weighted GATE EC/ECE area (Electronic Devices and VLSI) and compulsory in university VLSI Design and Semiconductor Devices papers. Interviewers at Intel, Qualcomm, AMD, NVIDIA, Samsung Semiconductor, TI, Micron, Synopsys, Cadence, Analog Devices, Microchip, SCL Mohali and Tata Electronics' Dholera fab use it to separate students who memorised the square-law equation from those who understand the physics.

Explained

Baseline: long-channel behaviour that scaling breaks

• The gradual-channel (Shockley) model assumes the vertical gate field controls inversion charge and the lateral drain field is much smaller — valid only when L is much greater than the source/drain depletion widths.
• Linear region (V_DS < V_GS − V_TH): I_D = µ_n C_ox (W/L)[(V_GS − V_TH)V_DS − V_DS²/2].
• Saturation: I_D = (µ_n C_ox/2)(W/L)(V_GS − V_TH)², with pinch-off at V_DSsat = V_GS − V_TH; I_D is ideally independent of V_DS.
• Threshold voltage: V_TH = V_FB + 2φ_F + Q_dep/C_ox, i.e. flat-band voltage + band bending for strong inversion + the charge in the depletion region. Oxide capacitance per unit area C_ox = ε_ox/t_ox.
• Body effect: a reverse source-to-body bias widens the depletion charge, raising V_TH — ΔV_TH = γ(√(2φ_F + V_SB) − √(2φ_F)).
• Subthreshold conduction: below V_TH the channel is in weak inversion and current is diffusion-driven and exponential in V_GS; the subthreshold swing S = (dV_GS/d log₁₀ I_D) has a thermal floor of 2.3 kT/q ≈ 60 mV/decade at 300 K, and real planar devices give 70–100 mV/decade. This floor is why V_TH (and therefore V_DD) cannot be scaled indefinitely.
• A device is called short-channel when L becomes comparable to the sum of the source and drain junction depletion depths — practically when any of the effects below shifts I_D or V_TH by more than about 10% from long-channel prediction.

Scaling theory: the three classical laws

• Full (constant-field) scaling — Dennard, 1974. Divide L, W, t_ox and junction depth by S; multiply doping by S; divide V_DD and V_TH by S. The electric field stays constant, so reliability is preserved.
  • Results per device: area ÷ S², capacitance ÷ S, delay ÷ S, current ÷ S, power ÷ S², power density unchanged, power-delay product ÷ S³, density × S².
  • This is the ideal case and the standard GATE/exam table.
• Constant-voltage scaling. Dimensions ÷ S but V_DD held fixed (needed for board-level compatibility, e.g. keeping 5 V TTL).
  • Field × S, current × S, power density × S³, delay ÷ S². Gives speed but the field rises — leading to oxide breakdown, hot-carrier damage and electromigration. Industry used this through the 5 V era and abandoned it.
• Quasi-constant-field / general scaling. Dimensions ÷ S, voltage ÷ U with U < S; the practical compromise actually used, because V_TH (and hence V_DD) is clamped by the 60 mV/decade subthreshold floor and by noise margins.
• Why Dennard scaling ended (~2005): V_TH could not fall further without exponential subthreshold leakage; V_DD stalled near 1 V; power density rose and gave the "power wall". Industry switched to equivalent scaling — strained silicon (90 nm), high-k metal gate (45 nm), FinFET/tri-gate (22 nm), FDSOI, nanosheet gate-all-around (2 nm class) — and to multicore rather than higher clocks.
• Modern node names (7 nm, 5 nm, 3 nm, 2 nm) are marketing labels, not physical gate lengths; physical gate length has been stuck in the 15–20 nm range for several generations.
• Scaling limits: direct tunnelling through oxide below ~1.5–2 nm SiO₂ (hence high-k), random dopant fluctuation and line-edge roughness causing V_TH mismatch, source-to-drain tunnelling, interconnect RC delay not scaling, and lithography/cost limits (EUV).

Short-channel effects, one by one

1. Channel length modulation (CLM). In saturation the pinch-off point moves towards the source as V_DS rises, shortening the effective channel, so I_D keeps rising: I_D = I_Dsat(1 + λV_DS). λ ∝ 1/L, so short devices have poor output resistance r_o = 1/(λI_D) and low intrinsic gain g_m·r_o — the central analog-design pain.
2. Threshold voltage roll-off (V_TH roll-off / charge sharing). The source and drain depletion regions share part of the depletion charge the gate would otherwise have to support, so the gate needs less voltage: V_TH falls as L falls, and the spread across a wafer worsens. Modelled by Yau's trapezoidal charge-sharing approximation.
3. Drain-induced barrier lowering (DIBL). The drain's field lowers the source-channel potential barrier, so V_TH decreases further as V_DS increases. Measured as DIBL coefficient η = −ΔV_TH/ΔV_DS in mV/V (good devices < 100 mV/V). It increases off-state leakage and degrades r_o beyond CLM.
4. Punchthrough. At very short L and high V_DS the drain and source depletion regions touch below the surface; current flows in the bulk out of the gate's control and rises almost without limit. Prevented by higher channel doping, retrograde/halo (pocket) implants, shallower junctions and SOI.
5. Velocity saturation. Carrier drift velocity saturates near v_sat ≈ 1 × 10⁷ cm/s for electrons in silicon once the lateral field exceeds E_c ≈ 1–4 × 10⁴ V/cm. Consequences: saturation starts earlier (V_DSsat < V_GS − V_TH); I_Dsat becomes linear, not quadratic, in (V_GS − V_TH) — I_Dsat ≈ W·C_ox·v_sat(V_GS − V_TH); and g_m saturates at W·C_ox·v_sat, independent of L, so making the device shorter stops buying transconductance.
6. Mobility degradation. The high vertical field pushes carriers against the oxide; surface roughness and phonon scattering cut effective mobility — µ_eff = µ₀/[1 + θ(V_GS − V_TH)].
7. Hot-carrier effects (HCE/HCI). The large peak lateral field near the drain gives carriers enough energy to (a) create electron-hole pairs by impact ionisation → substrate current, the standard monitor; (b) inject into the oxide, creating interface traps and trapped charge → V_TH drift, g_m loss, ageing; (c) at extremes trigger the parasitic lateral BJT and snapback/avalanche breakdown. Mitigated by LDD (lightly doped drain) / graded drain extension, which spreads the field, and by lower V_DD.
8. Subthreshold slope degradation and leakage. Short channels and DIBL raise S above 60 mV/decade, so I_OFF rises exponentially; leakage components are subthreshold, gate tunnelling, junction reverse and GIDL (gate-induced drain leakage) — band-to-band tunnelling at the gate-drain overlap when the gate is negative relative to the drain. Static power became comparable to dynamic power around the 90–65 nm nodes.
9. Narrow-width effect. For small W, the fringing depletion charge at the channel edges is extra charge the gate must support, so V_TH *rises* as W falls (opposite sign to roll-off). With LOCOS/STI edges, the reverse narrow-width effect can instead lower V_TH.
10. Reliability as a scaling issue. TDDB (time-dependent dielectric breakdown), NBTI in PMOS (V_TH drift under negative gate bias at temperature), PBTI in high-k NMOS, and electromigration in scaled interconnect — all worsen because fields rise faster than dimensions shrink.

Device and process fixes (what "equivalent scaling" means)

• LDD / drain extension: lightly doped n⁻ region between channel and n⁺ drain spreads the peak field — standard anti-hot-carrier measure, costs some series resistance.
• Halo / pocket implants and retrograde wells: locally raise doping near source and drain to suppress charge sharing, DIBL and punchthrough without raising body doping everywhere (which would hurt mobility and junction capacitance).
• Shallow junctions and silicided contacts: cut X_j to reduce the depletion encroachment term.
• High-k metal gate (HKMG), 45 nm onward: replace SiO₂ with HfO₂-based dielectric (k ≈ 20–25). A physically thicker film gives the same EOT = t_high-k × (ε_ox/ε_high-k) while cutting gate tunnelling by orders of magnitude; metal gates fix Fermi-level pinning and poly depletion. Gate-last/replacement-gate integration.
• Strained silicon: tensile strain for NMOS, compressive SiGe source/drain for PMOS, to recover mobility.
• SOI (PDSOI and FDSOI): a buried oxide cuts junction capacitance and, in fully depleted thin-film SOI, gives near-ideal S and strong SCE control with a back-gate V_TH tuning knob.
• Multigate devices: FinFET/tri-gate (gate wraps three sides of a fin; quantised width W ≈ 2H_fin + t_fin, so sizing is by fin count) and nanosheet gate-all-around (GAA) at the 2 nm class, where the gate surrounds the channel — best possible electrostatic control, S approaching 65–70 mV/decade, and much lower DIBL than planar.
• Beyond-CMOS steep-slope devices: tunnel FETs and negative-capacitance FETs aim below the 60 mV/decade limit; research-stage, not production.
• Design-level responses: multi-V_TH libraries, power gating, clock gating, DVFS, body biasing, stacked transistors for leakage, and always-on use of long-channel devices in analog current mirrors.

Indian context, standards and practice

• SI units throughout; device dimensions in nm, fields in V/cm or MV/cm, current normalised as µA/µm of channel width.
• Semiconductor Laboratory (SCL), Mohali (Department of Space) runs an indigenous 180 nm CMOS line — a genuinely long-channel-dominated node, which is why 180 nm design rules still appear in Indian academic tape-outs.
• India Semiconductor Mission (ISM) under MeitY, with the Semicon India programme approved in 2021 (₹76,000 crore outlay), supports fabs, OSAT/ATMP and design. Tata Electronics' Dholera fab with PSMC (Gujarat) and the Assam (Jagiroad) OSAT are the flagship projects; Micron's Sanand ATMP is in operation. Commercial output timelines have shifted more than once — treat any single start date as provisional.
• DLI (Design Linked Incentive) scheme and C-DAC/Chips-to-Startup (C2S) fund Indian academic and startup chip design; SHAKTI (IIT Madras) and VEGA (C-DAC) RISC-V processors were taped out on SCL 180 nm and on foreign advanced nodes respectively.
• PDK-level practice: foundry BSIM4 / BSIM-CMG compact models (Berkeley) carry all of these effects as parameters — DIBL (eta0), CLM (pclm), velocity saturation (vsat), mobility degradation (ua, ub, uc) — and BSIM-CMG is the industry-standard FinFET model. Students' SPICE answers must come from the PDK model, not the square law.
• Interview/exam convention: V_TH extraction by linear extrapolation of I_D–V_GS, or by the constant-current criterion I_D = 100 nA × (W/L) — state which you used.

Key points

• Scaling factor S — every linear dimension divided by S; density improves as S².
• Constant-field (Dennard) scaling — L, t_ox, V_DD all ÷ S, doping × S; power density constant, delay ÷ S, PDP ÷ S³.
• Constant-voltage scaling — dimensions ÷ S at fixed V_DD; field × S and power density × S³, so it is unreliable.
• Short-channel onset — when L approaches the sum of source and drain depletion widths plus junction depth.
• Channel length modulation — pinch-off point moves with V_DS; I_D = I_Dsat(1 + λV_DS), λ ∝ 1/L, kills output resistance.
• V_TH roll-off — charge sharing with S/D depletion regions lowers V_TH as L shrinks.
• DIBL — drain field lowers the source barrier, so V_TH falls as V_DS rises; quoted in mV/V.
• Punchthrough — merged source and drain depletion regions give uncontrolled bulk current; cured by halo implants and shallow junctions.
• Velocity saturation — v → v_sat ≈ 10⁷ cm/s; I_Dsat becomes linear in overdrive and g_m → W·C_ox·v_sat, independent of L.
• Subthreshold swing floor — 60 mV/decade at 300 K (2.3 kT/q); it is why V_TH and V_DD scaling stopped.
• Hot-carrier injection — impact ionisation near the drain creates substrate current and oxide traps; LDD is the standard fix.
• GIDL — band-to-band tunnelling at the gate-drain overlap, a key off-state leakage path.
• Narrow-width effect — V_TH rises as W shrinks because of edge depletion charge (opposite of roll-off).
• EOT — electrical thickness of a high-k film expressed as equivalent SiO₂; lets physical thickness grow to stop tunnelling.
• HKMG (HfO₂ + metal gate) — introduced at 45 nm to cut gate leakage and poly depletion.
• FinFET and GAA nanosheet — multigate electrostatics restore gate control; FinFET width is quantised in fins.
• Power wall — leakage and power density, not lithography, ended frequency scaling; multicore followed.
• Node names are marketing — "3 nm" is not a physical gate length.

Formulas and examples

Example 1 — Dennard scaling table (S = 2). A device has L = 180 nm, t_ox = 4 nm, V_DD = 1.8 V, I_D = 400 µA, delay 40 ps, dynamic power 80 µW. Apply ideal constant-field scaling with S = 2:

• L = 90 nm, t_ox = 2 nm, V_DD = 0.9 V.
• C ÷ 2 (area ÷ 4, t_ox ÷ 2 → C_ox × 2, so C = C_ox·W·L scales as 2 × ¼ = ½).
• I_D = 400/2 = 200 µA; delay = C·V/I = (½ × ½)/(½) = 40/2 = 20 ps.
• P = αCV²f: (½)(¼)(2) = ¼ → 80/4 = 20 µW — power ÷ S² as predicted.
• Power-delay product: 80 µW × 40 ps = 3.2 fJ → 20 µW × 20 ps = 0.4 fJ, i.e. ÷ 8 = ÷ S³. ✔
• Area per device ÷ 4, so power density = 20/(area/4) relative to 80/area → unchanged. ✔

Example 2 — same shrink under constant-voltage scaling. Keep V_DD = 1.8 V, S = 2:

• Field in oxide = 1.8 V/2 nm = 9 MV/cm, against 1.8/4 nm = 4.5 MV/cm before — above the ~10 MV/cm breakdown strength of SiO₂ in margin terms, which is exactly why this path was abandoned.
• Current × S: in the long-channel square law, I ∝ (W/L)C_ox V² = (1)(2)(1) → ×2 at the same voltage (W/L is unchanged, C_ox × 2) → 800 µA.
• Delay = CV/I = (½ × 1)/2 = ÷ 4 = 10 ps; power = CV²f with C ÷ 2, V fixed, f × 4 → × 2 = 160 µW in a quarter of the area (area ÷ S²) → power density × 8 = × S³, exactly the textbook figure.

Example 3 — subthreshold swing and leakage. t_ox = 2 nm, N_A = 1 × 10¹⁷ cm⁻³, L = 100 nm, W = 1 µm, 300 K.

• C_ox = 3.9 × 8.854 × 10⁻¹⁴/(2 × 10⁻⁷) = 1.73 × 10⁻⁶ F/cm² (17.3 fF/µm²).
• 2φ_F ≈ 0.84 V; W_d = √(2 × 1.036 × 10⁻¹² × 0.84/(1.6 × 10⁻¹⁹ × 10¹⁷)) ≈ √(1.088 × 10⁻¹⁰) ≈ 1.04 × 10⁻⁵ cm = 104 nm. (Already comparable to L — the device is firmly short-channel.)
• C_dep = 1.036 × 10⁻¹²/1.04 × 10⁻⁵ = 1.0 × 10⁻⁷ F/cm² → n = 1 + 0.10/1.73 ≈ 1.058.
• S = 2.3 × 0.0259 × 1.058 = 63 mV/decade (ideal-ish; real DIBL and traps push this to 80–100).
• If V_TH drops 150 mV from roll-off plus DIBL, leakage rises by 10^150/63 ≈ 10^2.4 ≈ 250×. This is the whole leakage story in one number.

Example 4 — velocity saturation versus square law. µ_eff = 300 cm²/V·s, v_sat = 10⁷ cm/s, V_GS − V_TH = 0.8 V, W = 1 µm, C_ox = 1.73 × 10⁻⁶ F/cm².

• E_c = v_sat/µ_eff = 10⁷/300 = 3.33 × 10⁴ V/cm.
• For L = 1 µm: E_c L = 3.33 × 10⁴ × 10⁻⁴ = 3.33 V ≫ 0.8 V → V_DSsat = 0.8 × 3.33/(0.8 + 3.33) = 0.645 V, close to the long-channel 0.8 V. Square law applies reasonably.
• For L = 0.1 µm: E_c L = 0.333 V → V_DSsat = 0.8 × 0.333/1.133 = 0.235 V, far below 0.8 V. The device saturates at a quarter of the classical voltage.
• Velocity-saturated current: I_Dsat ≈ W C_ox v_sat (V_GS − V_TH − V_DSsat) = 10⁻⁴ cm × 1.73 × 10⁻⁶ × 10⁷ × (0.8 − 0.235) = 1.73 × 10⁻³ × 0.565 ≈ 0.98 mA (980 µA/µm order, reduced further in practice by series resistance and mobility degradation).
• Square law for the same L: ½ × 300 × 1.73 × 10⁻⁶ × (1/0.1) × 0.8² = ½ × 300 × 1.73 × 10⁻⁶ × 10 × 0.64 = 1.66 mA — the square law overestimates by about 70%.

Example 5 — DIBL and output resistance. A 65 nm NMOS shows V_TH = 0.35 V at V_DS = 0.05 V and 0.29 V at V_DS = 1.0 V.

• η = (0.35 − 0.29)/(1.0 − 0.05) = 0.06/0.95 = 63 mV/V — acceptable for a planar 65 nm device.
• If I_D = 100 µA at V_DS = 0.6 V and λ = 0.2 V⁻¹, r_o = 1/(0.2 × 100 µA) = 50 kΩ; with g_m = 0.5 mS, intrinsic gain = 0.5 mS × 50 kΩ = 25 (≈ 28 dB) — against several hundred for a long-channel device, which is why analog designers deliberately use L of 2–10× minimum.

Where it is used

• Digital design and standard-cell libraries (Intel, AMD, Qualcomm, NVIDIA, Samsung, MediaTek India centres in Bengaluru, Hyderabad, Noida): multi-V_TH cell selection, leakage budgeting, power gating and sign-off at multiple corners are all direct consequences of SCE.
• Analog and mixed-signal / RF design (TI India, Analog Devices Bengaluru, NXP, Infineon, Cypress/Infineon Pune): channel-length modulation and low intrinsic gain drive cascoding, gain-boosting and non-minimum L choices; velocity saturation sets f_T.
• Device and TCAD engineering / process integration (SCL Mohali, Tata Electronics Dholera, Micron Sanand, IIT nanofabrication centres, CeNSE IISc): Sentaurus/Silvaco simulation of halo profiles, EOT and fin geometry, plus reliability qualification (HCI, NBTI, TDDB).
• Compact modelling and characterisation roles (foundry PDK teams, Synopsys, Cadence, Siemens EDA): extracting BSIM4/BSIM-CMG parameters for DIBL, CLM and velocity saturation from measured I–V data.
• Memory design (Micron, SanDisk/Western Digital Bengaluru): SRAM cell stability and DRAM retention are dominated by V_TH mismatch, subthreshold leakage and GIDL.
• Academic and ISM-funded tape-outs (C2S, DLI, SHAKTI/VEGA RISC-V cores): students designing at SCL 180 nm see long-channel behaviour, then compare against 28 nm/7 nm foundry PDKs where SCE dominates.

Interview questions

• Q: When is a MOSFET called short-channel? A: When the channel length becomes comparable to the source and drain depletion widths (and junction depth), so the drain field, not the gate alone, controls the channel and long-channel equations err by more than about 10%.
• Q: Difference between channel length modulation and DIBL? A: CLM is the shortening of the effective channel in saturation, which raises I_D with V_DS but does not change V_TH; DIBL is the drain field lowering the source barrier, which actually reduces V_TH as V_DS rises and raises off-state leakage.
• Q: Why is the 60 mV/decade subthreshold swing a fundamental limit? A: S = 2.3(kT/q)(1 + C_dep/C_ox); even with perfect gate coupling (C_dep/C_ox → 0) the thermal term 2.3 kT/q is 60 mV/decade at 300 K, because carriers follow a Boltzmann energy distribution.
• Q: Why did Dennard scaling stop? A: V_TH could not be lowered further without exponential subthreshold leakage, so V_DD stalled; with V_DD fixed, power density rose with density and gave the power wall.
• Q: How does velocity saturation change the saturation current? A: I_Dsat becomes roughly linear in (V_GS − V_TH) instead of quadratic, saturation starts at a much lower V_DS, and g_m saturates at W·C_ox·v_sat — independent of L.
• Q: Why high-k dielectric instead of simply thinner SiO₂? A: Below about 1.5–2 nm, direct tunnelling makes gate leakage unacceptable; a high-k film (HfO₂) gives the same EOT, hence the same C_ox and gate control, while being physically thick enough to suppress tunnelling.
• Q: What does a halo or pocket implant do? A: It raises doping locally near the source and drain to narrow their depletion regions, suppressing charge sharing, DIBL and punchthrough without degrading mobility and junction capacitance across the whole channel.
• Q: Why do analog designers avoid minimum channel length? A: λ ∝ 1/L, so short devices have low output resistance and low intrinsic gain g_m·r_o, plus worse V_TH mismatch and poorer matching — longer L buys gain and accuracy at the cost of speed and area.
• Q: What is GIDL and when does it matter? A: Band-to-band tunnelling in the drain under the gate-drain overlap when the gate is negative with respect to the drain; it dominates off-state leakage in low-V_GS, high-V_DS conditions and in DRAM retention.
• Q: How does a FinFET control short-channel effects better than a planar MOSFET? A: The gate wraps the channel on three sides (all sides in GAA), so gate capacitance dominates drain coupling; the thin, undoped fin is fully depleted, giving lower DIBL, steeper subthreshold slope and far less random dopant fluctuation.
• Q: Does V_TH increase or decrease when the channel is made shorter, and when the width is made narrower? A: It decreases with shorter L (roll-off from charge sharing) and increases with narrower W (extra edge depletion charge) — the two effects have opposite sign and partially cancel in small devices.
• Q: How would you detect hot-carrier degradation on a test structure? A: Monitor substrate current (a direct measure of impact ionisation) and stress the device at high V_DS, then track the shift in V_TH, g_m and I_Dsat over stress time to extrapolate lifetime.

Common mistakes

• Using the square-law saturation equation for a deep-submicron device, then wondering why SPICE gives roughly half the current — velocity saturation and mobility degradation must be included.
• Confusing CLM with DIBL, or saying DIBL "shortens the channel".
• Claiming that scaling V_DD and V_TH together always helps — it raises leakage exponentially and squeezes noise margins and gate overdrive.
• Getting the sign wrong: V_TH falls with shorter L but rises with narrower W.
• Mixing unit systems — ε in F/cm with t_ox in nm, or forgetting that C_ox is per unit area, which throws C_ox and I_D off by orders of magnitude.
• Taking node names literally ("3 nm means L = 3 nm") or quoting a FinFET's W as a continuous number rather than a multiple of fin count.
• Quoting a 60 mV/decade swing for a measured short-channel planar device; real devices are 80–100 mV/decade because of DIBL and interface traps.

Related topics

BJT and MOSFET · Semiconductor physics: energy bands, carriers and junctions · CMOS inverter and static/dynamic power · VLSI fabrication and CMOS process flow · Digital IC design and standard cells · Analog circuit design: gain stages and current mirrors