Physical design: floorplanning, placement, clock tree synthesis and routing

Electronics (VLSI Design) (B.E./B.Tech) · VLSI back end and test · free study notes for exams, placements and interviews

In short

Physical design (the "back end") turns a gate-level netlist into geometry on silicon: where every macro and standard cell sits, how power reaches it, how the clock is distributed and how every net is wired on metal layers. It is the stage where timing, area, power, congestion and manufacturability are actually met, so it decides whether a chip works at its target frequency. Universities examine it in VLSI Design / CAD for VLSI papers; GATE EC and CS ask placement-routing concepts, skew and delay arithmetic. It is the single largest employer of VLSI graduates in India - PD and timing engineers at Intel India, Qualcomm, Samsung SSIR, NVIDIA, AMD, Texas Instruments, Microchip, MediaTek, Synopsys, Cadence, Siemens EDA, Tata Elxsi, LTTS, eInfochips, Sankalp, SmartSoC and MosChip.

Explained

The flow and its inputs

Order of steps: netlist in → floorplan → power plan → placement → clock tree synthesis (CTS) → routing → parasitic extraction and timing closure → physical verification and signoff → GDSII/OASIS tape-out.
Inputs: gate-level Verilog netlist; .lib / Liberty timing and power models; LEF (abstract cell geometry, pin and blockage layers, metal pitch) with tech LEF (layer stack, design rules); SDC constraints (clocks, I/O delays, false/multicycle paths); floorplan DEF or a tcl floorplan script; IO/pad information; UPF for multi-voltage designs.
Outputs: DEF with placement and routing, SPEF parasitics, timing/power/DRC reports, and finally the stream-out layout.
PPA = power, performance, area - the three quantities every PD decision trades off.
Industry tools: Cadence Innovus, Synopsys IC Compiler II / Fusion Compiler, Siemens Aprisa; open-source OpenROAD/OpenLane is widely used in Indian academic projects and in the Chips-to-Startup (C2S) programme.

Floorplanning

Definition: fixing die and core size, placing I/O pads/bumps, placing hard macros (SRAMs, PLLs, ADCs, ROMs, IP), creating rows for standard cells, and building the power grid.
Die vs core: die = whole chip; core = region holding rows and macros; the gap between them holds the IO ring and power rings.
Utilization = occupied area / core area. Typical targets 60-75% at placement (leaves room for CTS buffers, routing and ECO cells); over ~85% causes congestion and timing failure.
Aspect ratio = core height / core width; 1 (square) is preferred unless the package or block shape dictates otherwise.
Macro placement rules of thumb: push macros to the periphery, keep their pins facing the core, group macros of the same bus/channel together, leave routing channels between macro arrays, keep a halo / keep-out margin so standard cells are not dropped into pin regions, and align macro pins to available metal tracks.
Blockages: *hard* (nothing placed), *soft* (global placement blocked, buffers allowed), *partial* (density limited, e.g. 40%), *routing* blockage (layer-specific). Used over macros and in congested corners.
Pin/port placement: for a block, pins are placed on the side nearest the driver/load in the parent, spread over feasible layers, to shorten top-level wires.
Power planning: core rings (top two thick metals), straps/stripes over the core, standard-cell rails (M1 follows the rows), vias/stacked vias joining them, and tap cells (n-well/p-substrate taps) at a rule-fixed spacing to prevent latch-up.
Physical-only cells: well taps, endcap/boundary cells at row ends, decap cells (local charge reservoir against dynamic IR drop), filler cells (added after routing to continue wells and implants), antenna diodes, spare cells for ECOs.
Quality checks: utilization, congestion map, macro-to-macro channel width, pin accessibility, PG grid completeness; a bad floorplan cannot be rescued by placement or CTS.
Partitioning (for very large SoCs): split into physical blocks, do each separately (hierarchical/bottom-up) and integrate at top level; flat flow is simpler but limited by tool runtime and memory.

Placement

Goal: legal, non-overlapping positions for all standard cells on rows, minimising wirelength and congestion while meeting timing and power.
Stages: (1) global placement - cells spread by analytical/quadratic or force-directed methods, overlaps allowed; (2) legalization - snap to rows and sites, remove overlaps with minimum displacement (Tetris/Abacus-style); (3) detailed placement - local swaps and shifts to improve wirelength, density and timing.
Cost metric: HPWL (half-perimeter wirelength) of each net's bounding box, summed - the standard objective because it is fast and correlates with real routed length.
Older algorithms examined in syllabi: min-cut/partition-based (Fiduccia-Mattheyses, Kernighan-Lin), simulated annealing (TimberWolf), force-directed; modern tools use analytical global placement.
Congestion-driven placement: the tool runs a trial/global route, builds a GCell congestion map and spreads cells where overflow appears; remedies are cell padding, partial blockages, density screens, lowering utilization, and spreading high-pin-count cells.
Timing-driven placement: net weights from pre-placement timing pull critical-path cells together; followed by in-place optimisation - buffer insertion, gate sizing, VT swap (HVT/SVT/LVT), cloning, logic restructuring.
Other placement-stage jobs: scan chain reordering (re-stitch scan order to the physical order to cut scan wirelength - the DFT structure itself is a separate topic), high-fanout net synthesis (HFNS) for resets and enables, placement of clock-gating cells near their register groups, spare-cell spreading.
Checks after placement: no overlaps/off-grid cells, density per region, pre-CTS setup timing (ideal clock), congestion overflow, max transition/capacitance.

Clock tree synthesis (CTS)

Why: up to placement the clock is *ideal* (zero delay). CTS builds a real buffered network from the clock source to every sink, since the clock is the highest-fanout, highest-activity net and typically 20-40% of dynamic power.
Definitions: insertion delay / latency = source-to-sink delay; skew = max latency − min latency among related sinks; local skew between launch and capture flops of a path is what timing actually cares about; global skew across the whole clock domain; jitter = cycle-to-cycle variation from the PLL/supply (a constraint input, not a CTS output).
Targets given to the tool: max skew, max latency, max transition on clock nets, max fanout per buffer, buffer/inverter list, NDR (non-default rules: double/triple width and double spacing, preferred mid-level metals) and shielding to resist crosstalk and EM.
Topologies: H-tree (balanced, symmetric, good for regular sink arrays), clock mesh/grid (very low skew, high power - CPUs), multi-level buffer tree (general ASIC default), clock spine. Inverter pairs are often preferred to buffers for better duty-cycle and transition control.
Clustering: sinks grouped by location and load; classic academic algorithms are MMM (method of means and medians), GMA (geometric matching) and DME (deferred-merge embedding, which gives zero-skew merging points).
Useful skew: deliberately delaying/advancing a capture clock to borrow time for a failing setup path, at the cost of hold margin - done by CTS or post-CTS via "clock skewing".
Clock gating: ICG cells inserted (usually in synthesis) and balanced during CTS; saves dynamic power but adds latency and skew to the branch.
Variation handling: OCV/derates, AOCV/POCV (depth- and distance-dependent), CRPR/CPPR (credit back the common clock path pessimism), and multi-corner multi-mode (MCMM) balancing so the tree works in all corners.
After CTS: clock is propagated; hold violations appear (now that real skew exists) and are fixed with delay buffers and sizing; setup is fixed with sizing/VT swap and useful skew. Report checks: skew, latency, transition, fanout, pulse width, clock-tree power, DRV violations.

Routing

Stages: (1) global routing - assign each net to a sequence of GCells/channels using a routing graph (maze/Lee's algorithm, line-search, A*, pattern routing L/Z/U-shaped), tracking supply vs demand; (2) track assignment - map segments to specific tracks and layers over long distances; (3) detailed routing - real wires and vias obeying all design rules; (4) search-and-repair - iterative rip-up and reroute of remaining violations.
Special routing comes first: power/ground, then clock nets with NDR and shielding, then signal routing.
Layer stack: M1 for intra-cell and rails, lower metals for short local nets, thick upper metals (lower resistance, larger pitch) for long nets, clock and power. Preferred direction alternates (e.g. M2 vertical, M3 horizontal). Tracks are the legal wire centre-lines, spaced by the metal pitch.
Routing resource per layer in a GCell = GCell width / pitch; overflow = demand − supply, the measure of congestion; a design with persistent overflow will not route cleanly.
Issues handled at routing: DRC (spacing, width, via rules, min-area, end-of-line), crosstalk/SI (coupling capacitance causing delay change and glitches - fixed by spacing, shielding, layer change, buffer insertion, driver upsizing), antenna effect (charge on a long floating metal damaging gate oxide during fabrication - fixed by bridging to a higher layer or adding antenna diodes), electromigration (current density limits → wider wires, more vias), double/multi-via insertion for yield, redundant via and wire spreading as post-route DFM steps, filler/metal fill for planarity, and colouring/double-patterning rules at 20 nm and below.
Post-route: extraction (SPEF), signoff STA with real RCs, ECO fixes (setup/hold, DRV), then physical verification and tape-out (covered in the signoff topic).
Limitations of the back end: wirelength and congestion are NP-hard - tools give heuristics, not optima; interconnect delay dominates gate delay below ~130 nm, so a poor floorplan cannot be recovered later; each iteration of the loop is hours to days of runtime on large blocks.

Indian context, standards and formats

Data standards are de-facto industry formats, not IS codes: LEF/DEF, Liberty (.lib/.db), SPEF, SDC, Verilog, GDSII and OASIS; foundry PDKs come under NDA.
Where Indian students get real PDKs: SCL Mohali's 180 nm line (used for academic and strategic tape-outs), the MeitY Chips to Startup (C2S) programme (28/65/180 nm access, academic tape-outs via C-DAC), and open PDKs (SkyWater 130 nm, GlobalFoundries 180 nm) with OpenLane.
Manufacturing in India is expanding under the India Semiconductor Mission (Micron ATMP at Sanand, a Tata-PSMC fab at Dholera and other approved units); schedules and capacities keep changing, so quote them only as announced plans.
Most Indian back-end work is design services and captive PD teams for foreign fabless companies - Bengaluru, Hyderabad, Noida/Greater Noida, Pune, Chennai, Ahmedabad.

Key points

Floorplanning - fixing die/core size, IO, macros, rows and power grid; the step that bounds everything after it.
Utilization - occupied area ÷ core area; 60-75% typical at placement so CTS and routing have room.
Aspect ratio - core height ÷ width; near 1 unless package or block shape forces otherwise.
Halo/keep-out - margin around a macro where standard cells are not placed, protecting pin access.
Blockage types - hard, soft, partial, routing; the standard tool for fixing local congestion.
Tap, endcap, decap, filler - physical-only cells for latch-up prevention, boundary rules, local charge and well continuity.
Global → legalization → detailed placement - spread, snap to rows, then refine for wirelength, density and timing.
HPWL - half-perimeter of a net's bounding box; the standard placement cost function.
Congestion/overflow - routing demand minus supply in a GCell; the real limit on utilization.
Scan reorder - re-stitching scan chains to physical order at placement to cut wirelength.
Insertion delay vs skew - source-to-sink latency vs the spread of latencies; timing depends on *local* skew.
CTS topologies - H-tree, mesh, multi-level buffer tree, spine; DME gives zero-skew merge points.
NDR and shielding - wider, well-spaced, shielded clock wires for low delay, low crosstalk, EM safety.
Useful skew - intentional skew that borrows time for setup at the cost of hold margin.
CRPR/OCV - pessimism removal on the common clock path, and derates for process variation.
Hold violations appear after CTS - because real skew and real clock delays replace the ideal clock.
Routing order - PG first, then clock, then signals; global → track assign → detailed → search-and-repair.
Antenna and EM - process-charge damage and current-density limits; fixed by diodes/layer jumps and wider wires with more vias.

Formulas and examples

Utilization U = (standard-cell area + macro area + physical-cell area) / core area (areas in µm²)
Standard-cell utilization = std-cell area / (core area − macro area − blockage area)
Core area required = total cell area / U_target ; Aspect ratio AR = H / W ; W = √(Area / AR), H = AR × W
HPWL(net) = (x_max − x_min) + (y_max − y_min) (µm)
Skew = t_insertion(max) − t_insertion(min) ; Clock period T = 1/f
Setup: T + t_skew ≥ t_cq + t_comb(max) + t_setup → setup slack = T + t_skew − (t_cq + t_comb,max + t_setup) (t_skew = capture arrival − launch arrival; the same signed skew is added to setup and subtracted in hold)
Hold: t_cq + t_comb(min) ≥ t_hold + t_skew → hold slack = (t_cq + t_comb,min) − (t_hold + t_skew)
Elmore/lumped wire delay of a uniform line: t = 0.5 R_total C_total = 0.5 (r L)(c L) = 0.5 r c L² (r in Ω/µm, c in fF/µm, L in µm)
Dynamic (switching) power P = α C V²f ; clock net α = 1 → P_clk = C_clk V² f (C in F, V in V, f in Hz, P in W)
Tracks per layer in a GCell = GCell width / metal pitch ; Overflow = demand − supply ; Congestion % = demand/supply × 100
H-tree with fanout k and N sinks: levels n = log_k N ; buffers = (kⁿ − 1)/(k − 1) ; insertion delay ≈ n × (t_buf + t_wire)
Antenna ratio = metal area (or perimeter) connected / gate-oxide area connected (must be below the foundry limit)

Example 1 - core size and aspect ratio. A block has 250,000 standard-cell instances of average area 1.8 µm² and macros totalling 150,000 µm². Target standard-cell utilization 70%.

Standard-cell area = 250,000 × 1.8 = 450,000 µm².
Row area needed = 450,000 / 0.70 = 642,857 µm²; add macros → core area = 642,857 + 150,000 = 792,857 µm².
Square core (AR = 1): side = √792,857 ≈ 890 µm × 890 µm.
If the package forces AR = 0.5 (wide block): W = √(792,857/0.5) = √1,585,714 ≈ 1,259 µm, H = 0.5 × 1,259 ≈ 630 µm.
Overall utilization = (450,000 + 150,000)/792,857 ≈ 75.7%.

Example 2 - utilization from a given floorplan. Core 1,000 µm × 800 µm, macros 200,000 µm², standard cells 360,000 µm².

Core area = 800,000 µm²; overall utilization = (360,000 + 200,000)/800,000 = 70%.
Standard-cell utilization = 360,000/(800,000 − 200,000) = 60% - comfortable, so there is room for CTS buffers and ECO cells.

Example 3 - clock tree sizing and power. 1,024 flops, buffer fanout limit 4, buffer delay 50 ps, average wire delay per level 30 ps, V = 0.9 V, f = 1 GHz, total clock-net + pin capacitance 50 pF.

Levels n = log₄1,024 = 5; buffers per level 1, 4, 16, 64, 256 → total = (4⁵ − 1)/3 = 1,023/3 = 341 buffers, the last 256 driving 4 sinks each = 1,024 sinks.
Insertion delay ≈ 5 × (50 + 30) = 400 ps.
Clock power = 50 × 10⁻¹² × 0.9² × 1 × 10⁹ = 50 × 10⁻¹² × 0.81 × 10⁹ = 40.5 mW (α = 1 for the clock).

Example 4 - setup and hold with real skew. f = 1 GHz → T = 1,000 ps. t_cq = 120 ps, t_comb(max) = 700 ps, t_comb(min) = 90 ps, t_setup = 80 ps, t_hold = 50 ps, capture clock arrives 60 ps *later* than launch (skew = 60 ps).

Setup: required = 120 + 700 + 80 = 900 ps; available = 1,000 + 60 = 1,060 ps → setup slack = +160 ps (late capture clock helps setup).
Hold: data arrives at 120 + 90 = 210 ps; required = 60 + 50 = 110 ps → hold slack = +100 ps.
If skew were reversed (capture 60 ps *early*): setup slack = 1,000 − 60 − 900 = +40 ps, hold slack = 210 − (50 − 60) = +220 ps - the same skew helps one check and hurts the other.

Example 5 - why long wires are buffered. r = 0.1 Ω/µm, c = 0.2 fF/µm, L = 10,000 µm.

Unbuffered: R = 1,000 Ω, C = 2 pF → t = 0.5 × 1,000 × 2 × 10⁻¹² = 1,000 ps.
Split into 5 segments of 2,000 µm with 4 buffers (buffer delay 30 ps): each segment R = 200 Ω, C = 0.4 pF → 0.5 × 200 × 0.4 × 10⁻¹² = 40 ps; total = 5 × 40 + 4 × 30 = 200 + 120 = 320 ps, a 3.1× improvement because wire delay falls as L².

Example 6 - routing congestion. GCell 10 µm wide, M3 pitch 0.10 µm, three horizontal layers available. Demand in that GCell = 330 tracks.

Supply per layer = 10/0.10 = 100 → total supply = 300; overflow = 330 − 300 = 30 tracks, congestion = 110% → reduce utilization, add a partial blockage or pad the cells there.

Stage	Objective	Main metric	Typical failure
Floorplan	Area, macro and PG structure	Utilization, channel width	Congestion, pin inaccessibility
Placement	Wirelength, timing, density	HPWL, overflow, pre-CTS slack	Congestion hotspots, max-cap/transition
CTS	Balanced clock delivery	Skew, latency, clock power	Hold violations, clock DRV
Routing	Legal, SI-clean wires	DRC count, overflow, post-route slack	Shorts, crosstalk delay, antenna

	Global routing	Detailed routing
Granularity	GCells / channels	Tracks, wires, vias
Rules	Capacity only	Full DRC
Speed	Fast, used inside placement	Slow, the long runtime step
Output	Net topology per region	Actual metal geometry

Where it is used

Fabless SoC and processor teams in India: PD/implementation engineers at Intel India, Qualcomm, NVIDIA, AMD, Samsung SSIR, Texas Instruments, Microchip, MediaTek, Marvell, Western Digital - mobile, GPU, automotive and storage SoCs.
Design-service companies: Tata Elxsi, LTTS, eInfochips, Sankalp Semiconductor, SmartSoC, Signoff Semiconductors, Wipro, HCLTech, Mirafra - block-level PD, timing closure and physical verification on customer PDKs.
EDA development: Synopsys, Cadence and Siemens EDA R&D centres in Bengaluru, Noida and Pune build the very placement, CTS and routing engines described here.
Strategic and public-sector silicon: SCL Mohali, C-DAC (VEGA processors), ISRO/DRDO ASICs, BEL - academic and strategic tape-outs at 180 nm and below.
Job roles: physical design engineer, PnR engineer, STA/timing closure engineer, CTS specialist, floorplan/chip-integration engineer, DFM/physical verification engineer; also memory and standard-cell layout roles.
Academic and start-up projects: OpenLane/OpenROAD RISC-V tape-outs under C2S and the DLI scheme at IITs, NITs and private universities.

Interview questions

Q: What is utilization and why not floorplan at 90%? A: Occupied area divided by core area; at very high utilization there is no room for CTS buffers, timing-ECO cells and routing tracks, so congestion and DRC violations make the block unroutable.
Q: Why do hold violations appear only after CTS? A: Before CTS the clock is ideal with zero delay and zero skew; CTS introduces real insertion delay and skew, so short data paths can now arrive before the capture clock edge.
Q: Difference between global skew and local skew? A: Global skew is the spread of latency across all sinks in a clock domain; local skew is between the launch and capture flops of one path - only local skew affects that path's setup and hold.
Q: What is useful skew? A: Deliberately delaying a capture clock (or advancing a launch clock) to give a failing setup path extra time, borrowed from the adjacent stage, at the cost of hold margin.
Q: Why are non-default rules and shielding used on clock nets? A: Wider, double-spaced and shielded clock wires reduce resistance, coupling-induced delay variation and crosstalk glitches, and meet electromigration limits on the highest-activity net.
Q: Why do we place macros at the periphery with pins facing the core? A: It keeps the centre free for standard-cell rows and routing, shortens macro-to-logic wires and avoids blocked routing channels and pin-access problems.
Q: What are tap cells and endcap cells for? A: Tap cells tie wells and substrate to supply rails at a rule-fixed spacing to prevent latch-up; endcap/boundary cells terminate rows so well and implant boundary rules are satisfied.
Q: How do you fix a congestion hotspot? A: Lower local utilization, apply cell padding or a partial placement blockage, spread high-pin-density cells, revisit macro channels and pin placement, change the floorplan or add a routing layer - not by rerouting harder.
Q: What is the antenna effect and how is it fixed? A: Charge collected on a long floating metal segment during plasma processing can rupture a connected gate oxide; fixed by breaking the segment with a jumper to a higher layer or attaching an antenna diode.
Q: Why does wire delay scale as L² and what follows from it? A: Both resistance and capacitance grow with length, so the RC product grows quadratically; therefore long nets are broken by repeaters, which makes delay roughly linear in length.
Q: What is CRPR/CPPR? A: Clock reconvergence pessimism removal - it credits back the pessimism of applying different derates to the clock path segment shared by launch and capture flops, which is physically the same wire.
Q: What is the difference between legalization and detailed placement? A: Legalization snaps overlapping global-placement cells onto legal rows and sites with minimum movement; detailed placement then does local swaps and shifts to improve wirelength, density and timing.
Q: Why are decap cells added and where? A: They act as local charge reservoirs that supply instantaneous switching current, reducing dynamic IR drop; they are placed near high-switching regions and clock buffers, with care because they add leakage.

Common mistakes

Confusing insertion delay with skew, or quoting global skew when the timing path needs local skew.
Writing the setup equation without the skew/clock-arrival term, or using the same sign of skew for both setup and hold.
Computing utilization against the die area instead of the core, or forgetting to subtract macro area for standard-cell utilization.
Believing routing or CTS can fix a bad floorplan - congestion and macro-channel mistakes must be fixed in the floorplan.
Mixing units: µm with mm in area, fF with pF in capacitance, ps with ns in delay - and then reporting slack that is out by 1,000×.
Assuming high fanout or long nets are a routing problem; they are placement and HFNS/buffering problems.
Forgetting tap, endcap, decap and filler cells, or inserting fillers before routing is complete.
Treating minimum-delay (hold) paths as unimportant - hold failure cannot be fixed by lowering the clock frequency, so it is a silicon kill.