PCB design and fabrication

In short

A printed circuit board is an insulating laminate carrying etched copper conductors that mechanically support and electrically connect components, replacing point-to-point wiring. Designing one means turning a schematic into a physical layout with correct track widths, clearances, pad shapes and layer stack-up, then exporting Gerber and drill files that a fabricator can manufacture. Fabrication is mainly a *subtractive* photolithographic and etching process on copper-clad laminate, followed by drilling, plating, solder mask, finish and assembly. B.Sc Electronics syllabi examine PCB types, the design flow, the full etching/plating sequence and soldering methods; questions appear in practical/viva, and in placement interviews at EMS and board houses such as Kaynes Technology, Syrma SGS, Dixon, Centum, BEL, PCB Power Market, Ascent Circuits, Shogini and Fine-Line Circuits, as well as in design-support and hardware-test roles.

Explained

What a PCB is - construction and types

• Base laminate: glass-fibre cloth impregnated with epoxy resin and cured - FR-4 is the standard grade (FR = flame retardant, relative permittivity εr ≈ 4.2-4.6 at 1 MHz, glass transition Tg ≈ 130-180 °C). Cheaper FR-2 (paper-phenolic, brown boards) and CEM-1 (paper core with woven-glass/epoxy faces) are used in low-cost consumer goods; polyimide for high temperature/flex; PTFE and ceramic-filled laminates (Rogers type) for RF/microwave; aluminium-backed (MCPCB) for LED lighting.
• Conductor: electrodeposited copper foil, specified by weight per square foot. 1 oz/ft² ≈ 35 µm thick, 2 oz ≈ 70 µm, 0.5 oz ≈ 17.5 µm.
• Standard board thickness: 1.6 mm (also 0.8, 1.0, 1.2, 2.0 mm). Standard panel sizes in Indian shops are 18" × 24" or 21" × 24".
• Types by layers: *single-sided* (copper on one face, jumpers needed), *double-sided* (both faces, joined by plated through holes), *multilayer* (4, 6, 8 … layers of copper separated by prepreg, with internal power/ground planes), *flexible* (polyimide), *rigid-flex*, *HDI* (microvias, laser-drilled).
• Other layers of a finished board: solder mask (green/other lacquer, prevents bridges and oxidation, leaves pads exposed), silkscreen/legend (white component references), surface finish on exposed copper.
• Interconnect features: track/trace (conductor), pad/land (solder site), via (plated hole joining layers: through via, blind via - outer to inner, buried via - inner to inner), annular ring (copper collar around a hole), thermal relief (spokes connecting a pad to a plane so it still solders), teardrop (fillet at pad-track junction), fiducial (optical alignment mark), mouse bite/V-groove (panel break-away).

Design flow - schematic to Gerber

1. Circuit design and component selection - electrical calculations, then availability and package choice (0603 vs 0805, SOIC vs QFN).
2. Schematic capture - draw the circuit in KiCad, EasyEDA, Eagle, OrCAD or Altium; annotate references (R1, C1, U1) and run ERC (electrical rules check) for unconnected pins, outputs shorted together.
3. Footprint/land-pattern assignment - each symbol gets a physical footprint per IPC-7351 land-pattern rules and the component datasheet's recommended land pattern.
4. Netlist generation - the machine-readable list of which pins belong to which net; it is imported into the PCB editor as a rat's-nest.
5. Board outline, mounting holes and mechanical constraints - connector positions, keep-out zones, enclosure fit.
6. Component placement - the step that decides routing quality: group by function, keep the crystal and decoupling capacitors next to the IC, place connectors at the edge, separate analogue from digital, heat sources away from sensitive parts.
7. Routing - manual, interactive or autorouted tracks on each layer, with design rules set first (minimum track, clearance, via size, annular ring).
8. Copper pour / planes, polygon fill, stitching vias, then DRC (design rule check) and netlist-vs-layout comparison.
9. DFM review - check against the fabricator's capability sheet (typical Indian prototype house: 0.15 mm track/gap, 0.3 mm drill, 0.15 mm annular ring).
10. Output files: Gerber RS-274X (one file per layer) or ODB++ / IPC-2581 (single data package), Excellon drill file, IPC-D-356 netlist for electrical test, centroid/pick-and-place file, BoM, assembly drawing.

Layout rules: tracks, clearance, vias, stack-up

• Track width is set by current (heating) and by resistance/voltage drop - computed with the IPC-2221 chart or formula; signal tracks are typically 0.2-0.3 mm, power tracks 1 mm and above.
• Clearance is set by voltage: IPC-2221B tables - roughly 0.1 mm for below 15 V on an uncoated internal/external layer, widening with voltage; mains-carrying boards need creepage/clearance from the safety standard for the product (IEC/IS 60950-type or IEC 62368-based), typically ≥ 3 mm live-to-live and ≥ 6 mm across reinforced insulation, with slots or ribs where the gap cannot be met.
• Hole and pad sizing: drill = lead diameter + 0.2-0.3 mm; pad diameter ≥ hole + 2 × minimum annular ring. Aspect ratio = board thickness / finished hole, kept ≤ 8:1 for reliable through-hole plating (≤ 10:1 in good shops).
• Vias: each via adds resistance and inductance; use several in parallel for current and for thermal paths under a QFN; do not place a via in a pad unless it is filled and capped (solder wicks away).
• Return current flows in the plane directly beneath the track at high frequency - never split a plane under a fast signal, and keep a continuous reference.
• Stack-up (4-layer, typical): signal / ground plane / power plane / signal - the ground plane next to the top signal layer gives controlled impedance and a low-inductance return.
• Controlled impedance: microstrip (track over one plane) and stripline (track buried between two planes); needed for USB (90 Ω differential), Ethernet, HDMI, DDR, RF (50 Ω).
• EMC/signal integrity practice: decoupling capacitor within a few millimetres of each supply pin, short loop area, no right-angle stubs on fast lines, guard/stitch vias around board edges, crystal shielded by ground, 3W rule for crosstalk-sensitive pairs.
• Thermal and mechanical: copper area as a heat spreader, thermal vias to the bottom plane, large pads for heavy parts, no tracks within ~0.5 mm of the board edge or under mounting screw heads.

Fabrication - subtractive process, step by step

1. Material cut - copper-clad laminate sheared to panel size, baked to remove moisture.
2. Drilling - CNC drilling of all through holes (0.2-6 mm) using carbide bits at 100,000+ rpm, several panels stacked with entry/exit boards; small holes (< 0.15 mm) are laser-drilled.
3. Deburr and desmear - permanganate or plasma removes resin smear from hole walls.
4. Electroless copper (hole metallisation) - a thin chemically deposited copper film makes the non-conductive hole wall conductive; this is what makes a plated through hole (PTH) possible.
5. Panel plating / pattern imaging - photoresist (dry film) is laminated, exposed through a photo-tool (or by direct imaging, LDI) and developed, so resist covers the copper that is to be kept in "print-and-etch" (the bare copper around it is etched away), or leaves the circuit pattern open in "pattern plating".
6. Electroplating - acid copper sulphate bath builds the copper in the holes and tracks to ~25 µm minimum hole-wall copper; a tin resist is then plated over the pattern.
7. Etching - the exposed copper is dissolved: ferric chloride or ammonium/cupric chloride (prototype and print-and-etch), alkaline ammoniacal etchant in plated-through-hole lines; tin resist is then stripped.
8. Multilayer sequence (extra steps): inner layers are imaged and etched first, oxide/bond treatment roughens the copper, then layers + prepreg are stacked and laminated in a hot press (~180 °C, high pressure), after which the panel is drilled and plated as above.
9. Solder mask - liquid photoimageable (LPI) mask is coated, exposed, developed and thermally cured.
10. Surface finish - HASL, ENIG, immersion tin/silver or OSP on exposed pads.
11. Legend printing - screen-printed or inkjet silkscreen, then cured.
12. Electrical test - bed-of-nails or flying-probe continuity and isolation test against the IPC-D-356 netlist.
13. Profiling - routing or punching to final outline, V-scoring for arrays; AOI, dimensional and microsection checks; packing with desiccant.
14. Additive/semi-additive processes (plating up on a seed layer) are used for HDI and fine lines; milling/isolation routing and toner-transfer are prototype-lab methods needing no etchant mask.
15. Etch factor / undercut: etching attacks the copper sidewall as well as the top, so thick copper needs wider designed tracks - etch factor = copper thickness / undercut per side (typically 2-4).

Surface finishes, assembly and soldering

• Through-hole (THT) components: leads inserted, wave-soldered or hand-soldered; strong mechanically, used for connectors, transformers, electrolytics.
• Surface mount (SMT): solder paste stencil-printed → pick-and-place → reflow oven (preheat ~150 °C, soak, peak ~245 °C for SAC305 lead-free, cool); allows both sides, small parts, automation.
• Mixed assembly: SMT reflow first, then selective/wave soldering of through-hole parts.
• Rework and inspection: hot-air station, soldering iron with temperature control (300-350 °C), X-ray for BGA joints, AOI for placement/polarity, ICT and functional test at the end.
• Defects to recognise: cold joint (dull, grainy), dry joint, solder bridge, tombstoning, insufficient fillet, voiding, lifted pad, delamination, measling, popcorning of moisture-sensitive parts (hence MSL bake before reflow).

Standards, statutes and Indian practice

• IPC standards govern practice worldwide and in Indian plants: IPC-2221/2222 (generic and rigid design), IPC-7351 (land patterns), IPC-6012 (rigid board performance), IPC-A-600 (board acceptability), IPC-A-610 (assembly acceptability - the one most quoted in EMS interviews), J-STD-001 (soldering requirements), IPC-2581/ODB++ (data transfer), IPC Class 1/2/3 = general / dedicated service / high-reliability (medical, aerospace).
• BIS publishes Indian Standards on printed wiring boards and on laminates, and electronics products come under the Electronics and IT Goods (Compulsory Registration) Order - the BIS registration mark on consumer electronics; quote an IS number only after checking its current edition, as several older PCB-related IS numbers have been revised or withdrawn.
• Hazardous-substance limits in India are set by the E-Waste (Management) Rules, 2022 (in force from 1 April 2023), which carry RoHS-type restrictions - lead, mercury, hexavalent chromium, PBB, PBDE ≤ 0.1% by weight in homogeneous material and cadmium ≤ 0.01% - and make producers responsible for take-back with EPR targets; this is why lead-free SAC solder and lead-free HASL are standard.
• Effluents: etching and plating lines are water-polluting; discharge is consented and monitored by the State Pollution Control Board under the Water (Prevention and Control of Pollution) Act, 1974, with copper/nickel limits and mandatory recovery - prototype labs must not pour spent ferric chloride down the drain.
• Worker safety in a fabrication plant now falls under the four Labour Codes in force from 21 November 2025, with the Occupational Safety, Health and Working Conditions Code replacing the Factories Act, 1948 - hazardous-chemical handling, ventilation, PPE and health checks for plating/etching areas.
• Industry support: PLI schemes for large electronics manufacturing and for electronic components (including PCBs/laminates), SPECS and the India Semiconductor Mission's ATMP/OSAT push; most Indian bare-board capacity is single/double-sided and 4-6 layer, with HDI and high-layer-count boards still largely imported. PCBs attract GST under the 18% slab in the structure effective 22 September 2025 - confirm the HSN-wise rate before quoting.

Key points

• PCB - insulating laminate with etched copper conductors that both support and interconnect components.
• FR-4 - glass-epoxy laminate, εr ≈ 4.3, the default material; 1.6 mm is the standard thickness.
• 1 oz copper - 35 µm thick; copper weight, not thickness, is how it is ordered.
• Subtractive process - unwanted copper is etched away; additive/semi-additive plates it up and is used for HDI.
• PTH - plated through hole; made conductive by electroless copper, then built up by electroplating to ≥ 25 µm wall copper.
• Gerber + Excellon - the layer artwork and drill data a fabricator needs; ODB++/IPC-2581 package everything in one file.
• ERC vs DRC - ERC checks the schematic electrically, DRC checks the layout against physical rules.
• Track width - set by current and ΔT via IPC-2221; clearance is set by working voltage.
• Aspect ratio - board thickness ÷ finished hole; keep ≤ 8:1 for plating reliability.
• Annular ring - (pad dia − hole dia)/2; too small a ring breaks out when drilling drifts.
• Solder mask and silkscreen - mask prevents bridging and oxidation; silkscreen carries legends only.
• Microstrip/stripline - controlled-impedance structures; impedance depends on w, h, t and εr, not on length.
• Decoupling capacitor placement - as close to the supply pin as possible; loop inductance, not capacitance, decides performance.
• Ground plane - gives a short return path, lowers impedance and EMI; never split it under a fast signal.
• SMT vs THT - SMT is reflow-soldered, dense and automated; THT is wave/hand-soldered and mechanically stronger.
• Reflow profile - preheat, soak, reflow (peak ≈ 245 °C for lead-free), cool; wrong profile causes cold joints or tombstoning.
• IPC-A-610 Class 2 vs Class 3 - normal service versus high-reliability acceptance criteria.
• E-Waste (Management) Rules, 2022 - the Indian route for RoHS-type substance limits and producer take-back.

Formulas and examples

Example 1 - Track width for a 3 A supply rail (outer layer, 1 oz, ΔT = 10 °C)

• ΔT^0.44 = 10^0.44 = 2.754; k·ΔT^0.44 = 0.048 × 2.754 = 0.1322.
• I/0.1322 = 3/0.1322 = 22.69; A = 22.69^1/0.725 = 22.69^1.379 ≈ 74.3 mil².
• W = 74.3 / (1.378 × 1) ≈ 54 mil = 1.37 mm. On an inner layer (k = 0.024) halving k raises the required area by 2^1.379 ≈ 2.6 times, to about 193 mil², and the width becomes about 3.6 mm - internal traces cannot shed heat.

Example 2 - Resistance and drop in that rail

• Take W = 0.5 mm, t = 35 µm, L = 50 mm, I = 2 A. Cross-section = 0.5 × 10⁻³ × 35 × 10⁻⁶ = 1.75 × 10⁻⁸ m².
• R = 1.72 × 10⁻⁸ × 0.05 / 1.75 × 10⁻⁸ = 0.049 Ω (49 mΩ).
• Check by squares: R_s = 1.72 × 10⁻⁸ / 35 × 10⁻⁶ = 0.491 mΩ/square; L/W = 50/0.5 = 100 squares → 49 mΩ. ✔
• Drop = 2 × 0.049 = 98 mV; dissipation = 2² × 0.049 = 0.196 W. For a 3.3 V rail a 98 mV drop is 3% - acceptable; for a 1.2 V core rail it is not, so widen the track.

Example 3 - 50 Ω microstrip on FR-4 (εr = 4.3, 1 oz copper)

• 87/√(4.3 + 1.41) = 87/2.390 = 36.41. Need ln(...) = 50/36.41 = 1.373 → 5.98h/(0.8w + t) = e^1.373 = 3.95.
• With a thin 0.2 mm dielectric: 5.98 × 0.2 = 1.196; 0.8w + 0.035 = 1.196/3.95 = 0.303 → w = 0.335 mm.
• With a plain 1.6 mm two-layer board: 5.98 × 1.6 = 9.568; 0.8w + 0.035 = 2.424 → w = 2.99 mm - which is why RF and high-speed designs use a 4-layer stack with a thin top dielectric instead of a 1.6 mm two-layer board.
• Delay of a 15 cm microstrip, ε_eff ≈ 3.1: t_pd = 33.36 × 1.761 = 58.7 ps/cm → 0.88 ns (relevant for DDR and clock skew budgets).

Example 4 - Etchant needed for a prototype

• Board 100 mm × 80 mm = 0.008 m² of 1 oz copper, 70% of it etched away.
• Copper volume = 0.008 × 0.7 × 35 × 10⁻⁶ = 1.96 × 10⁻⁷ m³ = 0.196 cm³ → mass = 0.196 × 8.96 = 1.76 g.
• FeCl₃ required = 1.76 × 324.4/63.5 ≈ 9 g (stoichiometric; in practice 2-3 times more, as the bath is used until the copper loading saturates). The spent liquor is a copper-bearing effluent and must go to an authorised recycler.

Example 5 - Panel utilisation, aspect ratio and cost

• Panel 457 × 610 mm (18" × 24"), 12.5 mm border all round → usable 432 × 585 mm. Board 100 × 80 mm.
• Orientation A: 432/100 = 4 across, 585/80 = 7 down → 28 boards. Orientation B: 432/80 = 5, 585/100 = 5 → 25 boards. Choose A.
• If the fabricator charges ₹2,800 per double-sided panel, cost ≈ ₹100 per board before assembly; this is why a tiny design and a large one cost nearly the same in prototype quantities.
• Aspect ratio for a 0.3 mm hole in a 1.6 mm board = 1.6/0.3 = 5.3:1 - well inside the 8:1 limit. With a 0.15 mm hole it becomes 10.7:1 and needs an HDI/microvia process.
• Annular ring for a 0.8 mm pad on a 0.4 mm hole = (0.8 − 0.4)/2 = 0.2 mm - acceptable; on a 0.6 mm pad it is 0.1 mm, at the limit of most Indian prototype shops.

Where it is used

• EMS and board fabrication: Kaynes Technology (Mysuru), Syrma SGS, Dixon, Centum, Ascent Circuits, PCB Power Market (Gandhinagar), Shogini, Fine-Line Circuits - roles in CAM engineering, process (plating/etching), AOI/test and SMT line operation.
• Defence, space and railways: BEL, ISRO/VSSC suppliers, DRDO labs and railway signalling vendors demand IPC Class 3 boards with coupon microsections and conformal coating.
• Consumer and lighting: LED drivers and bulbs on aluminium MCPCBs, inverter and UPS boards, fan regulators, set-top boxes - mostly single/double-sided FR-2 or FR-4.
• Product start-ups and labs: KiCad/EasyEDA design, prototypes from Indian and overseas quick-turn houses, bring-up and debugging with multimeter, oscilloscope and hot-air rework.
• Repair, service and field roles: reading a board, tracing nets, desoldering and replacing SMD parts on mobile, TV and instrument boards.
• Academic and training work: university labs still teach toner-transfer/photoresist single-sided fabrication and ferric chloride etching, which is where viva questions come from.

Interview questions

• Q: Why is PCB copper specified in ounces? A: It is the weight of copper spread over one square foot; 1 oz/ft² corresponds to about 35 µm thickness, and the foil is manufactured and sold by weight.
• Q: What makes a through hole conductive before electroplating? A: A thin electroless (chemically deposited) copper film on the drilled resin wall, which gives the surface the conductivity needed for electrolytic plating.
• Q: What decides the width of a power track? A: The current and the acceptable temperature rise (IPC-2221), and separately the acceptable voltage drop from R = ρL/Wt - whichever demands more width.
• Q: Does the length of a trace change its characteristic impedance? A: No - Z₀ depends on the cross-section geometry (w, t, h) and εr; length affects propagation delay and loss, not impedance.
• Q: Why is a ground plane preferred over a ground track? A: It offers a minimum-inductance return path right under every signal, reduces loop area and EMI, and helps spread heat.
• Q: What is aspect ratio and why does it matter? A: Board thickness divided by finished hole diameter; a high ratio makes it hard for plating solution to deposit even copper in the hole, so the barrel can crack in thermal cycling.
• Q: Difference between a blind via and a buried via? A: A blind via connects an outer layer to an inner layer only; a buried via connects inner layers and is not visible from either surface.
• Q: Why should a via not be placed inside an SMD pad? A: Molten solder wicks down the hole, starving the joint - unless the via is filled with resin and capped (via-in-pad).
• Q: What is tombstoning and what causes it? A: A small two-terminal SMD standing on one end during reflow, caused by unequal pad sizes or heating, uneven paste or unbalanced thermal relief.
• Q: HASL or ENIG for a board with a 0.4 mm pitch BGA? A: ENIG - its surface is flat and planar, whereas HASL's uneven solder domes cause coplanarity and bridging problems at fine pitch.
• Q: What files do you send a fabricator and an assembler? A: Fabrication: Gerber (or ODB++/IPC-2581), Excellon drill, stack-up and fab notes; assembly: BoM, centroid/pick-and-place file, assembly drawing and paste-layer data.
• Q: Which Indian rules restrict lead in electronics, and what is the consequence for soldering? A: The E-Waste (Management) Rules, 2022 cap lead at 0.1% in homogeneous materials, so assembly uses lead-free SAC alloys with a higher melting point (~217 °C) and peak reflow near 245 °C.

Common mistakes

• Treating copper weight as thickness, or mixing mil (0.0254 mm) with millimetres in track-width and clearance calculations.
• Using the outer-layer constant k = 0.048 for an internal trace - inner layers carry roughly half the current for the same width.
• Sizing a track only for current and ignoring voltage drop, which is what actually fails low-voltage, high-current rails.
• Forgetting the annular ring and minimum drill when shrinking pads, so holes break out of their pads on the real board.
• Autorouting without first setting design rules, defining the stack-up and placing components sensibly - placement, not routing, decides a layout's quality.
• Putting decoupling capacitors anywhere on the net instead of beside the supply pin, and splitting the ground plane under fast signals.
• In the lab: under-etching (copper bridges left), over-etching (thin or broken tracks), handling ferric chloride without gloves/eye protection, and pouring spent etchant into the sink.

Related topics

• Electronic instruments: CRO and multimeter · Soldering, assembly and SMD rework practice · Power supplies and voltage regulators · Digital electronics and microcontroller hardware · EMI/EMC and signal integrity basics · CAD tools: KiCad and Gerber data.