Multilevel inverters

Electrical and Electronics Engineering (B.E./B.Tech) · Power electronics and drives · free study notes for exams, placements and interviews

In short

A multilevel inverter synthesises its AC output as a staircase of many small voltage steps instead of switching the whole DC voltage in one jump, by splitting the DC link (or using several isolated DC sources) across series-connected devices. Because each device blocks only a fraction of the DC voltage, the topology reaches medium voltage and beyond (3.3–11 kV drives, up to ±320 kV HVDC) with available IGBTs/IGCTs while cutting harmonic distortion, dv/dt and EMI, and it does this at low switching frequency, so losses stay low. It is the standard converter for medium-voltage drives, central solar PV and wind converters, STATCOMs, VSC-HVDC links and modern traction. In India it is examined in GATE EE (power electronics), in university power-electronics and drives papers, and it is asked at BHEL, Hitachi Energy, Siemens, ABB, Danfoss, Delta, Tata Power, Power Grid, Adani and Indian Railways/RDSO interviews.

Explained

Why go multilevel

Device voltage limit: silicon IGBT/IGCT blocking voltage is practically capped near 6.5 kV, and must be derated; a two-level inverter puts the full DC voltage across one device, so it cannot reach medium voltage without series strings that need exact static and dynamic voltage sharing.
Stress sharing: in an *m*-level converter each switch blocks only Vdc/(m−1), so standard 1.7 kV or 3.3 kV devices serve a 6.6 kV or 11 kV output.
Lower dv/dt: the output jumps one step (Vdc/(m−1)) at a time, reducing motor insulation stress, reflected-wave overvoltage on long cables, bearing currents and common-mode EMI.
Better waveform at lower switching frequency: more steps plus carrier interleaving pushes the first significant harmonic group to a higher order and lowers THD, so the filter shrinks and switching loss falls — important above a few MW where f_sw is only a few hundred hertz.
Cost: many more devices, gate drives, sensors, isolated supplies and a more complex controller; justified only where voltage, power or waveform quality demands it.
Terminology: *m* levels means *m* distinct steps in the phase (pole-to-neutral) voltage; the line voltage then has 2m−1 levels. A conventional bridge is the 2-level case.

Diode-clamped (NPC) inverter

The DC link is split by (m−1) series capacitors; clamping diodes tie the mid-points to the switch string, so each pole can be connected to any tap.
Three-level NPC (the workhorse): four switches and two clamping diodes per leg; output states +Vdc/2, 0, −Vdc/2 obtained from switch pairs (S1S2), (S2S3), (S3S4). S2 and S3 are the "inner" switches that create the zero state.
Counts per phase leg (m levels): 2(m−1) switches, (m−1)(m−2) clamping diodes, (m−1) DC capacitors shared by all three phases.
Limitations: clamping-diode count grows as m², diodes need series strings and have unequal reverse-blocking duty; neutral-point (DC capacitor) voltage drifts because the mid-point carries a third-harmonic ripple current; device loss distribution is uneven. Rarely built beyond five levels.
Neutral-point balancing: inject zero-sequence/common-mode offset, choose between redundant small vectors in SVPWM, or use a closed loop on the measured capacitor voltages.
ANPC (active NPC): replaces clamping diodes with active switches, giving extra commutation paths that equalise loss sharing and allow higher output current; used in modern MV drives and large PV inverters.
T-type / NPP (neutral-point-piloted): a two-level leg plus a bidirectional switch to the mid-point; only that branch needs half-voltage devices. Very popular at 1000–1500 V DC in string and central PV inverters because conduction loss is lower at low switching frequency.

Flying-capacitor (capacitor-clamped) inverter

Clamping is done by floating capacitors charged to graded voltages (Vdc/(m−1), 2Vdc/(m−1), …) instead of diodes.
Counts per phase: 2(m−1) switches, (m−1)(m−2)/2 flying capacitors, plus (m−1) DC-link capacitors.
Redundant switching states let the same output level be made in several ways, which is used to charge or discharge each flying capacitor — self-balancing with phase-shifted carriers (natural balancing).
Limitations: many bulky capacitors, pre-charging circuitry needed at start-up, no inherent fault tolerance, and capacitor voltage ripple sets the switching frequency floor. Mostly seen in stacked multicell drives and some high-frequency DC–DC/filter applications.

Cascaded H-bridge (CHB) inverter

Each phase is a series string of *s* single-phase full bridges (H-bridges), each fed by its own isolated DC source; cell output is +Vdc, 0, −Vdc, so phase levels = 2s+1.
Counts per phase: 4s = 2(m−1) switches, s = (m−1)/2 isolated DC sources, no clamping diodes, no clamping capacitors.
Symmetric CHB: all sources equal; modular, identical cells, easy to extend, cell-level bypass gives fault tolerance (ride through with a shorted cell plus neutral-shift control).
Asymmetric CHB: unequal sources raise levels sharply — binary 1:2:4 gives 2^s+1−1 levels (3 cells → 15), trinary 1:3:9 gives 3^s levels (3 cells → 27). Penalty: non-identical cells, hybrid devices and modulation, uneven power sharing.
DC source problem: isolated sources need a multi-winding phase-shifting transformer (standard for 11 kV CHB drives, which also gives multi-pulse rectifier input with low line-current THD), or they come naturally from PV strings, battery modules or fuel cells — hence CHB in grid-tied PV and battery energy-storage converters.
A CHB STATCOM needs no DC source at all (capacitors only), as it exchanges mainly reactive power; individual cell-capacitor voltage balancing is then the core control task.

Modular multilevel converter (MMC)

Each of the six arms is a series chain of *N* submodules (SMs), each a half-bridge (cap inserted or bypassed) or full-bridge (also gives −Vc, allowing DC-fault blocking and DC voltage reversal) with its own floating capacitor.
Arm voltage has N+1 levels; Vdc = N·Vc (nominal). With N in the hundreds the output is almost sinusoidal — no AC filter, very low dv/dt, and an average switching frequency per device of only about 100–150 Hz (a few switchings per fundamental cycle).
Control layers: (1) outer current/power control; (2) arm energy and circulating (second-harmonic) current suppression; (3) capacitor-voltage balancing/sorting that picks which SMs to insert; (4) redundant SMs for availability.
Submodule capacitor energy is typically of the order of 30–40 kJ per MVA (design dependent); this dominates converter volume.
Dominant topology for VSC-HVDC, large STATCOMs and some MV motor drives; needs start-up pre-charge resistors and careful DC-fault strategy (half-bridge MMC cannot block DC-side faults).

Modulation and control methods

Level-shifted (carrier-disposition) PWM: (m−1) triangular carriers stacked in amplitude, one reference per phase; variants PD (phase disposition — best line-voltage THD), POD and APOD (alternate phase opposite disposition). Natural choice for NPC/FC.
Phase-shifted carrier PWM: s = (m−1)/2 carriers of equal amplitude displaced by 360°/s in CHB, or (m−1) carriers displaced by 360°/(m−1) in FC; shares power equally among cells and gives natural capacitor balancing. Each cell switches at f_c but the string's effective ripple frequency is s·f_c.
Selective harmonic elimination (SHE-PWM) / staircase modulation: one switching angle per level per quarter cycle; solve nonlinear equations to set the fundamental and null chosen low-order non-triplen harmonics (5th, 7th, 11th, 13th). Lowest switching loss — standard for high-power CHB and early NPC drives.
Space-vector PWM: the *m*-level hexagon has 3m(m−1)+1 vectors and many redundant states; redundancy is spent on capacitor balancing and common-mode reduction. Computation grows with m, so MMCs use nearest-level control (NLC) instead.
Over-modulation and third-harmonic/min-max injection raise the usable line voltage by about 15% (as in two-level inverters).
Modulation index for stacked carriers: m_a = A_ref / [(m−1)·A_carrier/2]; frequency ratio m_f = f_carrier/f_ref.

Standards and Indian practice

Harmonics: IEEE 519 (2022 edition) is the reference for voltage distortion and current TDD limits; the CEA (Technical Standards for Connectivity to the Grid) Regulations, 2007 and its amendments adopt IEEE 519-type limits for grid-connected plant, and the CEA (Technical Standards for Connectivity of the Distributed Generation Resources) Regulations, 2013 cap grid-tied inverter current THD at about 5% with individual-harmonic sub-limits. Exact clause values have been amended more than once — check the current gazette version.
Solar inverters: safety and performance to IS/IEC 62109-1 and -2, grid interface per CEA/state DISCOM regulations and CEIG approval; MNRE's ALMM framework lists approved modules and (as notified in phases) inverters — the scope and dates have shifted, so verify the live MNRE order.
General converter safety/EMC: IEC 62477-1 (power electronic converter systems), IEC 61800-3/IEC 61800-5-1 for adjustable-speed drives, IEC 61000 series for EMC.
Traction: RDSO specifications for three-phase propulsion equipment on WAG-9/WAP-7 class locomotives and EMU/Vande Bharat stock, which use 3-level NPC (or two-level with 6.5 kV devices) GTO/IGBT traction converters.
HVDC: IEC 62747 (terminology and level/distortion definitions for VSC) and IEC 62501 for VSC valve testing (the IEC 60700 series covers thyristor valves).

Key points

Multilevel inverter - synthesises AC as a staircase of m steps; each device blocks only Vdc/(m−1).
Level count - *m* levels in phase voltage ⇒ 2m−1 levels in line voltage.
NPC/DCMLI - split DC link plus clamping diodes; 2(m−1) switches, (m−1)(m−2) diodes, (m−1) capacitors per leg.
Flying capacitor - clamping by floating capacitors, (m−1)(m−2)/2 per phase; self-balancing with phase-shifted carriers but capacitor-heavy.
Cascaded H-bridge - s = (m−1)/2 isolated-source H-bridges per phase; modular, fault-tolerant, needs isolated DC sources.
MMC - N submodules per arm, N+1 arm levels, Vdc = N·Vc; the HVDC/STATCOM standard.
Asymmetric CHB - binary 1:2:4 → 2^s+1−1 levels; trinary 1:3:9 → 3^s levels.
Neutral-point drift - the NPC mid-point carries third-harmonic current; needs active balancing or zero-sequence injection.
Redundant switching states - the surplus states that make capacitor-voltage balancing possible at all.
Level-shifted PD-PWM - best line-voltage harmonic performance for NPC/FC; phase-shifted PWM equalises cell power in CHB.
SHE-PWM - one angle per level kills selected low-order harmonics at minimum switching frequency.
dv/dt - reduced by factor (m−1) versus two-level for the same DC voltage; protects motor insulation and cuts EMI.
THD - falls roughly as 1/(m−1) for comparable modulation; filter size and cost fall with it.
ANPC and T-type - loss-optimised three-level legs; T-type dominates 1000/1500 V PV inverters.
Efficiency - 3-level NPC drives typically 98–99%, MMC converter stations above 99% per station.
Cost driver - device, gate-drive, sensor and capacitor count, plus control complexity, not the silicon area alone.
Common-mode voltage - three-level legs give smaller CMV steps; further reduced by selecting zero-CMV vectors.
Grid code - Indian grid-connected converters must meet CEA connectivity regulations referencing IEEE 519-type harmonic limits.

Formulas and examples

Device blocking voltage: V_sw = Vdc/(m−1) [V]; output step size = Vdc/(m−1)
Phase-voltage levels = m; line-voltage levels = 2m−1
NPC per phase leg: switches = 2(m−1); clamping diodes = (m−1)(m−2); DC-link capacitors = (m−1)
FC per phase leg: switches = 2(m−1); flying capacitors = (m−1)(m−2)/2
CHB per phase: cells s = (m−1)/2; switches = 4s = 2(m−1); isolated DC sources = s
SPWM line voltage (linear range): V_LL,rms = (√3/(2√2))·m_a·Vdc = 0.6124·m_a·Vdc [m_a ≤ 1]
Staircase (SHE) fundamental, symmetric CHB: V_1,peak = (4Vdc/π)·Σ_{k=1..s} cos α_k [α_k = switching angles, deg]
nth harmonic: V_n,peak = (4Vdc/nπ)·Σ_{k=1..s} cos(n α_k), n odd
Modulation index (staircase): m_a = π·V_1,peak/(4·s·Vdc); (stacked carriers): m_a = A_ref/[(m−1)A_c/2]
THD = √(Σ_{n≥2} V_n²)/V_1 ; WTHD = √(Σ (V_n/n)²)/V_1
MMC: Vdc = N·V_c ; arm levels = N+1 ; submodules per converter = 6N ; IGBTs (half-bridge SM) = 12N
Asymmetric CHB levels: binary = 2^s+1 − 1 ; trinary = 3^s
dv/dt ≈ [Vdc/(m−1)]/t_r [V/s, t_r = device switching transition time]

Example 1 — Five-level NPC for a 3.3 kV drive. Target V_LL = 3.3 kV rms with m_a = 0.95 → Vdc = 3300/(0.6124 × 0.95) = 3300/0.5818 = 5672 V; choose Vdc = 5.6 kV.

Capacitor/step voltage = 5600/(5−1) = 1400 V; each switch blocks 1400 V → 3.3 kV IGBTs (≈42% utilisation, safe).
Phase-voltage steps: 0, ±1400, ±2800 V (5 levels); line voltage has 2×5−1 = 9 levels.
Count per leg: switches 2(5−1) = 8 → 24 total; clamping diodes (4)(3) = 12 → 36 total; DC-link capacitors 4 (shared).
Achieved output: 0.6124 × 0.95 × 5600 = 3258 V rms line.
dv/dt at t_r = 1 µs: 1400 V/µs against 5600 V/µs for a two-level bridge on the same DC link — a 4× reduction.

Example 2 — Seven-level symmetric CHB, staircase modulation. m = 7 → s = (7−1)/2 = 3 cells per phase, 9 isolated DC sources, 4×3×3 = 36 switches. Cell voltage Vdc = 200 V.

Equal-area (half-height) angles with the reference peak set to the maximum step s·Vdc: α_k = arcsin[(2k−1)/(2s)] → α₁ = arcsin(1/6) = 9.59°, α₂ = arcsin(3/6) = 30.00°, α₃ = arcsin(5/6) = 56.44°.
Σcos α_k = 0.9860 + 0.8660 + 0.5528 = 2.4048.
V_1,peak = (4 × 200/π) × 2.4048 = 254.65 × 2.4048 = 612.4 V (staircase m_a = π·612.4/(4×3×200) = 0.80).
Phase rms = 612.4/√2 = 433.1 V; line rms = 433.1 × √3 = 750.2 V (note the fundamental peak exceeds the 600 V maximum step, exactly as a square wave's fundamental exceeds Vdc).

Example 3 — SHE-PWM on a five-level CHB (eliminate the 5th harmonic). m = 5 → s = 2 angles. Required: V_1 set by m_a = 0.8 and V_5 = 0.

Equations: cos α₁ + cos α₂ = 2 m_a = 1.6 ; cos 5α₁ + cos 5α₂ = 0.
Solving numerically: α₁ ≈ 14.75°, α₂ ≈ 50.75° (check: cos14.75 + cos50.75 = 0.9670 + 0.6330 = 1.600 ✓; cos73.75 + cos253.75 = 0.2800 − 0.2800 ≈ 0 ✓).
Fundamental: V_1,peak = (4Vdc/π)(1.6) = 2.037 Vdc. With Vdc = 500 V per cell → V_1,peak = 1018 V, phase rms 720 V, line rms 1247 V.
The 5th is nulled; the 7th, 11th and 13th remain and are filtered or handled by adding more cells (s angles can set the fundamental and remove s−1 harmonics).

Example 4 — MMC for a ±320 kV VSC-HVDC link. Pole-to-pole Vdc = 640 kV; submodule capacitor voltage V_c = 1.6 kV.

N = 640,000/1600 = 400 submodules per arm; arm voltage levels = 401; submodules per converter = 6 × 400 = 2400; half-bridge IGBTs = 12 × 400 = 4800 (plus redundant SMs, typically a few per cent).
Maximum AC output at m_a = 1: V_LL,rms = 0.6124 × 640 kV = 392 kV, so an interface transformer matches it to the 400 kV grid with margin for reactive capability.
At 2000 MW and 0.95 power factor on a 400 kV bus, converter AC current ≈ 2000×10⁶/(√3 × 400×10³ × 0.95) = 3040 A rms.
Stored energy at 35 kJ/MVA ≈ 35 × 2000 = 70 MJ per station — the physical size driver.

Example 5 — Asymmetric versus symmetric CHB (3 cells per phase).

Scheme	Cell voltages	Step	Phase levels	Max phase step
Symmetric	100, 100, 100 V	100 V	2(3)+1 = 7	300 V
Binary	100, 200, 400 V	100 V	2(700/100)+1 = 15	700 V
Trinary	100, 300, 900 V	100 V	3³ = 27	1300 V

Same 12 switches per phase; the binary scheme more than doubles levels and the trinary nearly quadruples them, but cells are no longer interchangeable and the high-voltage cell switches at fundamental frequency while the low-voltage cell does the PWM (hybrid modulation).

Feature	NPC (3-level)	Flying capacitor	CHB	MMC
Isolated DC sources	No (single DC link)	No	Yes, s per phase	No
Clamping elements	Diodes, (m−1)(m−2)	Capacitors, (m−1)(m−2)/2	None	SM capacitors
Modularity / scaling	Poor beyond 5 levels	Moderate	Excellent	Excellent
Capacitor balancing	Neutral-point control needed	Natural with PS-PWM	Per-cell control	Sorting algorithm
Fault tolerance	Low	Low	Cell bypass	Redundant SMs
Typical use	MV drives, PV, traction	Stacked multicell drives	11 kV drives, STATCOM, PV/BESS	HVDC, large STATCOM

Where it is used

Medium-voltage industrial drives: 3.3 kV/6.6 kV/11 kV VFDs on ID and FD fans, boiler feed pumps, mill drives and compressors in NTPC, Tata Steel, JSW, UltraTech and refinery projects — supplied by Siemens, ABB/Hitachi, Danfoss, TMEIC, BHEL (3-level NPC, ANPC and 11 kV CHB cells).
VSC-HVDC: the Pugalur (Tamil Nadu)–Thrissur (Kerala) ±320 kV, 2000 MW link uses MMC converters (commissioned in stages from about 2021; confirm the latest status with Power Grid), and MMC is the default for new offshore/renewable-corridor links.
Solar PV and storage: 1500 V DC central and string inverters almost universally use 3-level T-type or NPC legs (Sungrow, SMA, TMEIC, Delta, Hitachi, Waaree inverters deployed at Bhadla, Pavagada and Rewa solar parks); CHB appears in large battery-storage converters.
STATCOM and power-quality equipment: MMC/CHB STATCOMs on state transmission systems and in steel plants and railway traction substations for flicker and reactive compensation; SVG panels for wind farms.
Traction: three-phase propulsion converters on Indian Railways WAG-9/WAP-7 locomotives, EMU/MEMU and metro stock (Delhi, Chennai, Kochi, Mumbai) use 3-level NPC or equivalent IGBT inverters; RDSO specifications govern them.
Job roles: power-electronics design engineer (topology, loss and thermal calculation), control/firmware engineer (modulation, balancing, FPGA/DSP), test and validation engineer, HVDC/FACTS commissioning engineer, solar plant design and grid-compliance engineer.

Interview questions

Q: Why use a multilevel inverter instead of a two-level inverter? A: Each device blocks only Vdc/(m−1), so medium-voltage output is possible with available devices, and the staircase output gives lower THD, dv/dt and EMI at a much lower switching frequency.
Q: How many levels does the line voltage have if the phase voltage has 5 levels? A: 2m−1 = 9 levels, because the line voltage is the difference of two phase voltages.
Q: Why is the NPC topology rarely built beyond five levels? A: Clamping diodes grow as (m−1)(m−2), their blocking duty is unequal, and DC-link capacitor voltage balancing becomes practically impossible with real load power flow.
Q: What is neutral-point voltage drift and how is it fixed? A: The NPC mid-point carries a third-harmonic ripple current that unbalances the two DC capacitors; it is corrected by injecting a zero-sequence/common-mode component or by choosing between redundant small SVPWM vectors under closed-loop capacitor control.
Q: Why does a cascaded H-bridge inverter need isolated DC sources? A: The cells are series-connected on the AC side, so a common DC source would short-circuit through the cells; isolation comes from a multi-winding transformer, PV strings or battery modules.
Q: Which modulation gives the best line-voltage THD for an NPC inverter? A: Phase-disposition level-shifted PWM, because the carriers are in phase and the common-mode components cancel in the line-to-line voltage.
Q: Why is phase-shifted carrier PWM preferred for CHB and flying-capacitor converters? A: It distributes switching and power equally among the cells and naturally balances the clamping/cell capacitors, while multiplying the effective ripple frequency.
Q: In SHE-PWM with s switching angles, how many harmonics can you control? A: s equations, so one sets the fundamental and s−1 selected non-triplen harmonics are eliminated (triplen harmonics cancel in a balanced three-wire line anyway).
Q: What decides the number of submodules per MMC arm? A: N = Vdc/V_c, the DC voltage divided by the chosen submodule capacitor voltage (set by the device rating and derating), plus redundant modules for availability.
Q: Why can a half-bridge MMC not clear a DC-side fault, and what helps? A: Its antiparallel diodes form an uncontrolled rectifier path from the AC side; full-bridge or clamp-double submodules can insert negative voltage and block the fault, otherwise AC breakers or DC circuit breakers are needed.
Q: Does a multilevel inverter switch faster or slower than a two-level one? A: Slower — each device switches at a few hundred hertz (or fundamental frequency in staircase/MMC schemes), because the waveform quality comes from the number of levels, not the carrier frequency.
Q: Why do solar inverters favour the T-type three-level leg? A: At 1000–1500 V DC with moderate switching frequency it has lower conduction loss than NPC (only one high-voltage device in the main path) while keeping three-level output and half-voltage mid-point devices.
Q: Which Indian regulation sets harmonic limits for a grid-connected inverter? A: The CEA connectivity regulations (2007 for grid connectivity, 2013 for distributed generation), which reference IEEE 519-type voltage and current distortion limits; exact clause values have been amended, so the current gazette text must be checked.

Common mistakes

Confusing phase-voltage levels with line-voltage levels, and quoting m instead of 2m−1 for the line waveform.
Misquoting the component formulas — writing (m−1) clamping diodes instead of (m−1)(m−2) for NPC, or forgetting that the (m−1) DC-link capacitors are shared by all three phases while flying capacitors are per phase.
Assuming a multilevel inverter needs a higher switching frequency; the whole point is good waveform quality at low f_sw.
Treating capacitor voltage balancing as automatic — it is a designed control loop in NPC and MMC, and only partly natural in flying-capacitor and phase-shifted-PWM schemes.
Using V_LL,rms = 0.612·m_a·Vdc beyond m_a = 1 without noting over-modulation, or forgetting the ≈15% gain from third-harmonic injection.
Giving a single DC bus to a cascaded H-bridge in a circuit diagram — an instant fail in vivas and interviews.
Sizing devices for Vdc rather than Vdc/(m−1), or conversely ignoring the derating factor (devices are used at roughly 50–60% of rated blocking voltage).
In SHE problems, forgetting the constraint 0 < α₁ < α₂ < … < 90° and accepting a mathematically valid but unrealisable angle set.