Logic synthesis and low-power design

In short

Logic synthesis converts RTL (Verilog/VHDL/SystemVerilog) into a gate-level netlist of standard cells from a target technology library, optimised for timing, area and power under user constraints. Low-power design is the set of RTL, synthesis and architectural techniques that cut dynamic switching power and leakage power, specified today through UPF (IEEE 1801) power intent. Together they form the heart of the "front-end" job in Indian VLSI service and product companies — Synopsys, Cadence, Qualcomm India, Intel India, Samsung SRI-B, Texas Instruments, NXP, Nvidia, MediaTek, Bosch, Sankalp/Einfochips/Tessolve — and are the standard interview filter for an RTL-to-GDS or synthesis engineer. In exams they appear in VLSI Design, Low Power VLSI and ASIC Design papers, and in GATE EC under digital/CMOS power and delay.

Explained

What synthesis is and how a tool does it

• Definition: logic synthesis = translation + optimisation + technology mapping. Input: RTL + constraints (SDC) + technology library (.lib/Liberty, compiled as .db); output: gate-level netlist + timing/area/power reports.
• Three classical stages:
• Translation (elaboration): RTL is parsed into a technology-independent intermediate — GTECH/generic gates, and arithmetic as DesignWare-style operators. Inference happens here: always @(posedge clk) → flop, always @(*) with incomplete assignment → latch.
• Logic optimisation: technology-independent Boolean restructuring — two-level minimisation, multi-level factoring, kernel extraction, resource sharing, constant propagation, redundancy removal, finite-state-machine state minimisation and re-encoding.
• Technology mapping: the Boolean network is covered by actual library cells (AND2_X1, DFFRPQ_X4…) choosing drive strengths and Vt flavours to meet timing at least area/power. Then incremental fixes: buffer insertion, cell upsizing/downsizing, cloning, logic duplication, DRC fixes (max fanout, max transition, max capacitance).
• Two optimisation styles: *flattening* (collapse multi-level logic into two-level sum-of-products — good for small random logic) and *structuring* (extract common factors — smaller area, more levels, slower).
• Synthesis effort/flow modes: simple compile vs. incremental/high-effort compile; topographical / physically-aware synthesis (Design Compiler Topographical, Genus iSpatial) uses a floorplan to estimate real wire loads instead of statistical wire-load models, which drastically reduces post-layout timing surprises.
• Hierarchical choices: compile each block separately and preserve boundaries (set_dont_touch), or ungroup/flatten hierarchy to optimise across boundaries. Flattening gives better QoR; hierarchy gives runtime, reuse and easier debug. Boundary optimisation pushes constants through ports.

Constraints, libraries and the quality checks

• Mandatory SDC: create_clock (period, waveform), set_clock_uncertainty (jitter + skew margin), set_input_delay / set_output_delay, set_driving_cell, set_load, set_max_fanout / set_max_transition, set_clock_latency, operating conditions and set_operating_conditions corner.
• Exceptions: set_false_path (logically impossible / asynchronous crossing), set_multicycle_path, set_max_delay / set_min_delay, set_case_analysis, set_disable_timing. Over-use of false paths is the commonest way engineers hide real bugs.
• Library content (Liberty): cell function, pin capacitance, NLDM/CCS delay and transition tables (indexed by input slew and output load), setup/hold constraint tables, leakage_power per state, internal_power (short-circuit + internal node switching) tables, max_capacitance, area, and PVT corner header (e.g. SS 0.81 V 125 °C, TT 0.9 V 25 °C, FF 0.99 V −40 °C).
• Synthesis is performed at the worst setup corner (slow library, low voltage, high temperature) and hold is usually fixed in physical implementation at the fast corner; leakage is worst at FF/high temperature.
• Deliverable checks: no unresolved references, no latches inferred unintentionally, no combinational loops, no multiple-driven nets, DRC-clean (max fan-out/transition/cap), WNS/TNS within target, and formal equivalence (LEC) between RTL and netlist using Conformal/Formality — mandatory sign-off because synthesis rewrites logic.
• Design-for-test insertion during or after synthesis: scan-flop substitution, scan stitching, test clock, set_scan_configuration; scan adds area and a mux delay in the data path.

Writing RTL that synthesises well

• Use **non-blocking (<=) for sequential, blocking (=) for combinational**; mixing them in one block causes simulation-synthesis mismatch.
• Full case with default, complete if-else, and full sensitivity (always @(*) / always_comb) prevent unintended latches.
• Unsupported for synthesis: initial blocks (except FPGA RAM init), delays #10, fork-join, real/time types, hierarchical references, $display-type system tasks.
• Avoid multiple drivers, gated or derived clocks written by hand (use library clock-gating cells), asynchronous feedback, and arithmetic in the middle of a long combinational chain.
• Reset style: synchronous reset is cheaper and filters glitches; asynchronous reset works without a clock but needs a reset synchroniser and recovery/removal checks.
• Coding affects QoR: if-else chains infer priority (long, serial) logic; case infers a parallel mux. Pipeline or register-balance long paths at RTL — a tool cannot invent architecture.

Where power goes: the three components

• Dynamic (switching) power — charging and discharging load capacitance: P = α·C·V²·f. The dominant term in active logic; quadratic in supply voltage.
• Short-circuit (internal) power — both nMOS and pMOS conduct during the input transition; typically 5–15% of dynamic power, worsened by slow input slew.
• Static (leakage) power — subthreshold conduction (I ∝ exp(−V_th/(n·V_T)), V_T = kT/q), gate-oxide tunnelling, reverse-bias junction and GIDL leakage. Leakage grows exponentially as Vth falls and with temperature, and at advanced nodes (sub-28 nm, FinFET) can be 20–40% of total chip power; it is why multi-Vt libraries and power gating exist.
• Power vs. energy: power (W) matters for thermal/IR-drop design; energy per operation (J) matters for battery life. Lowering frequency alone cuts power but not energy per operation; lowering voltage cuts both.

Low-power techniques by design level

• Architecture/system: parallelism and pipelining to allow voltage reduction; memory hierarchy to avoid long high-capacitance accesses; hardware accelerators instead of CPU loops; DVFS (dynamic voltage and frequency scaling) with OS/power-management-IC control; AVS using on-chip process monitors.
• RTL/logic:
• Clock gating — the single highest-return technique; the clock tree and flops can be 30–50% of dynamic power. Tools insert integrated clock-gating (ICG) cells (latch + AND) automatically where an enable exists; the latch prevents enable glitches. *Fine-grain* (per flop group) and *coarse-grain* (per block) gating.
• Operand isolation / data gating — AND the inputs of an unused arithmetic block with its valid signal so it stops toggling.
• Glitch reduction — balance path delays, use balanced tree arithmetic instead of long ripple chains; glitches are real toggles that burn real power.
• Encoding — Gray code for counters and address buses (one bit changes), one-hot for fast FSMs, bus-invert coding for wide off-chip buses.
• Memory banking / sleep — split RAM and enable only the addressed bank.
• Gate/cell level: multi-Vt mapping (HVT on slack-rich paths, SVT default, LVT only on critical paths), cell downsizing on non-critical paths, logic restructuring to put high-activity nets on low-capacitance pins (pin swapping), multi-bit flops to share the clock driver and reduce clock power and area.
• Power gating (MTCMOS) — a high-Vt header (pMOS, on VDD) or footer (nMOS, on VSS) switch disconnects an idle block, cutting leakage by orders of magnitude. Needs: isolation cells to clamp floating outputs, retention flops (always-on shadow latch) to save state, always-on buffers, a power switch chain with ack daisy chain, and a controlled wake-up sequence to limit rush current. Cost: area, wake-up latency, energy break-even time.
• Multi-voltage (multi-VDD) — separate voltage areas; level shifters at crossings (low→high needs an LS; high→low can use a simple buffer in many libraries) and enable level shifters where both shifting and isolation are required.
• Other: substrate/body biasing, dual-rail/sub-threshold logic for ultra-low-power IoT, adiabatic logic (academic), SOI/FinFET process help.

UPF power intent and the low-power flow

• IEEE 1801 (UPF) is the standard, tool-independent description of power intent kept outside the RTL, so one RTL serves many power configurations. UPF 3.x adds system-level power modelling.
• Core commands: create_power_domain, create_supply_port/net/set, create_power_switch, set_isolation + set_isolation_control, set_level_shifter, set_retention + set_retention_control, add_port_state, create_pst / add_pst_state (legal state table), set_domain_supply_net.
• Flow: RTL + UPF → synthesis inserts ISO/LS/retention/switches → netlist + updated UPF → P&R builds power grid, always-on routing and switch chain → verification by low-power static checks (Spyglass-Power / VC LP) and power-aware simulation plus power-aware LEC.
• Power estimation accuracy chain: RTL vector-free (activity propagation, ±20–30%) → gate-level with SAIF/VCD from simulation (PrimePower, Joules, ±10–15%) → post-layout with real parasitics and signoff IR-drop analysis (Redhawk/Voltus).
• Indian practice note: these are international EDA/IEEE standards, not BIS standards; the relevant Indian institutional context is MeitY's Chips-to-Startup/SMDP and the India Semiconductor Mission's EDA-tool access and shuttle (SCL Mohali 180 nm) for academic tape-outs, and BIS energy-labelling applies to the finished electronic product, not the netlist.

Key points

• Logic synthesis — RTL → optimised technology-mapped gate netlist under SDC constraints and a Liberty library.
• Three stages — translation/elaboration, technology-independent optimisation, technology mapping with incremental fix-up.
• Liberty (.lib) — cell delay/transition, power and constraint tables per PVT corner; the tool's only view of silicon.
• Topographical synthesis — uses a floorplan for real wire loads; wire-load models are statistical and optimistic.
• Flatten vs. preserve hierarchy — flattening gives better timing/area, hierarchy gives runtime and reuse.
• Unintended latch — caused by incomplete if/case in combinational blocks; the classic synthesis bug.
• Formal equivalence (LEC) — mandatory RTL-vs-netlist proof after synthesis and after any ECO.
• P_dynamic = α·C·V²·f — voltage is the strongest lever because of the square term.
• Leakage — subthreshold + gate tunnelling + GIDL; exponential in Vth and temperature; worst at the FF/hot corner.
• Clock gating — biggest single dynamic-power saving; ICG cell = latch + AND to avoid enable glitches.
• Multi-Vt — HVT (low leakage, slow), SVT, LVT (fast, leaky); mix per-path by slack.
• Power gating (MTCMOS) — header/footer switch + isolation + retention + always-on; trades wake-up latency for leakage.
• Multi-VDD — needs level shifters at domain crossings and a legal power state table (PST).
• DVFS — scale V and f with workload; cubic-order saving in power for a given task class.
• UPF (IEEE 1801) — power intent outside RTL, consumed by synthesis, P&R and verification.
• Activity factor α — switching probability per clock; it, not just capacitance, decides dynamic power.
• Energy per operation vs. power — battery life depends on energy; thermal and IR limits depend on power.
• Glitches are power — unbalanced combinational paths burn energy without changing the result.

Formulas and examples

Example 1 — dynamic power of a bus. A 32-bit data bus, each line C = 120 fF, V_DD = 0.9 V, f = 500 MHz, average activity α = 0.15 per line per cycle.

• Per line: P = 0.15 × 120×10⁻¹⁵ × 0.81 × 500×10⁶ = 0.15 × 120×10⁻¹⁵ × 4.05×10⁸ = 7.29×10⁻⁶ W = 7.29 µW.
• 32 lines: P ≈ 233 µW (0.233 mW).
• Switch to Gray-coded addressing so α drops to 0.05: P = 32 × 2.43 µW = 77.8 µW — a 66.7% saving on this bus.

Example 2 — voltage scaling vs. frequency scaling. A block runs at V₁ = 1.0 V, f₁ = 400 MHz, P₁ = 50 mW (ignore leakage).

• (a) Halve frequency only: P = 50 × (200/400) = 25 mW, but the task takes twice as long → energy per task unchanged (50 mW × T vs 25 mW × 2T).
• (b) Scale to V₂ = 0.8 V and f₂ = 320 MHz: P₂ = 50 × (0.8/1.0)² × (320/400) = 50 × 0.64 × 0.8 = 25.6 mW.
• Energy per task in (b) = P₂ × (400/320)T = 25.6 × 1.25 = 32 mW·T vs 50 mW·T → 36% energy saving, because V fell. Lesson: only voltage reduction saves energy per operation.

Example 3 — clock gating. A design has 20,000 flops; clock-network + flop-clock-pin power = 180 mW of a 400 mW total. 70% of the flops are in blocks whose enable is high only 25% of cycles. ICG overhead = 4 mW.

• Gated clock power = 180 × 0.70 = 126 mW; after gating it becomes 126 × 0.25 = 31.5 mW.
• Saving = 126 − 31.5 − 4 = 90.5 mW.
• New total = 400 − 90.5 = 309.5 mW, i.e. a 22.6% chip-level reduction from one RTL technique.

Example 4 — multi-Vt leakage trade-off. A block has 100,000 cells; LVT leakage = 60 nA/cell, SVT = 12 nA/cell, HVT = 2.5 nA/cell at V_DD = 0.9 V. Timing analysis shows only 8% of cells are on critical paths, 30% have moderate slack, 62% have large slack.

• All-LVT: I = 100,000 × 60 nA = 6.0 mA → P = 0.9 × 6.0 mA = 5.40 mW.
• Mixed (8% LVT, 30% SVT, 62% HVT): I = 8,000×60 + 30,000×12 + 62,000×2.5 nA = 480,000 + 360,000 + 155,000 = 995,000 nA = 0.995 mA → P = 0.9 × 0.995 mA = 0.896 mW.
• Leakage cut by 83.4% with the same timing closure — the standard answer to "how do you fix a leakage violation in synthesis?"

Example 5 — power-gating break-even. A block leaks 2 mW when idle. Waking it costs 150 nJ (rush current + state restore) and 8 µs of latency.

• T_be = 150×10⁻⁹ J / 2×10⁻³ W = 75×10⁻⁶ s = 75 µs.
• So power gate only if the idle window exceeds ~75 µs (plus the 8 µs latency must be acceptable to the system). Shorter idles are better served by clock gating.

Where it is used

• ASIC/SoC front-end teams in Qualcomm, Intel, Nvidia, AMD, Samsung SRI-B, Texas Instruments, NXP, MediaTek, Marvell and Micron India — synthesis engineer, RTL design engineer, low-power/power-architecture engineer.
• Design-service companies — Einfochips, Tessolve, Sankalp, L&T Technology Services, Cyient, HCLTech, Wipro, Tata Elxsi — RTL-to-netlist handoff, UPF-based low-power implementation and ECO work.
• Battery-driven products — smartphone APs, wearables, Bluetooth/BLE and Wi-Fi SoCs, smart meters, hearables: clock gating plus power gating plus multiple always-on and sleep domains define the product's standby current.
• Automotive and industrial — Bosch, Continental, Marelli and ISRO/DRDO/SCL work: safety-critical RTL with scan insertion, derated libraries and strict leakage budgets for high-temperature (125–150 °C) operation.
• EDA vendors in India — Synopsys (Bengaluru/Noida/Hyderabad), Cadence, Siemens EDA: R&D on synthesis engines, Liberty/UPF support and power-analysis tools.
• Academic and startup tape-outs — MeitY Chips-to-Startup and India Semiconductor Mission programmes give institutes EDA access and SCL Mohali 180 nm shuttles; synthesis and UPF scripting is the skill actually exercised there.

Interview questions

• Q: What are the inputs and outputs of logic synthesis? A: Inputs are RTL, SDC constraints, the technology library (.lib/.db) and optionally UPF and a floorplan; outputs are a gate-level netlist plus timing, area and power reports and an updated SDC/UPF.
• Q: Why is dynamic power proportional to V² but leakage only roughly linear in V? A: Dynamic power is the energy C·V² moved per switching event; leakage is V_DD times a leakage current whose dominant dependence is exponential in V_th and temperature, not on V_DD squared.
• Q: Why does an integrated clock-gating cell contain a latch? A: The latch samples the enable while the clock is low, so a late or glitching enable cannot create a partial clock pulse at the gated output.
• Q: Does clock gating reduce leakage? A: No — it only stops toggling, so it cuts dynamic power; the cells remain powered, so leakage is unchanged. Power gating is the leakage remedy.
• Q: How do you fix a leakage violation without breaking timing? A: Swap slack-rich cells to higher-Vt variants and downsize them, keep LVT only on critical paths, and consider power gating for blocks that are idle longer than the break-even time.
• Q: Where is a level shifter needed and where is it not? A: At a crossing from a lower to a higher supply a level shifter is essential, since the low signal cannot fully turn off the receiving pMOS; high-to-low crossings are often safe with a buffer in the receiver's domain, but library rules decide.
• Q: What do isolation and retention cells do in a power-gated design? A: Isolation cells clamp the outputs of a shut-down domain to a known value so always-on logic does not see floating inputs; retention flops keep state in an always-on shadow latch so the block need not be re-initialised on wake-up.
• Q: Why is formal equivalence checking mandatory after synthesis? A: Synthesis rewrites logic (restructuring, re-encoding, constant propagation, clock gating insertion), so simulation alone cannot prove the netlist still implements the RTL; LEC proves functional equivalence point by point.
• Q: Your synthesis timing is clean but post-layout timing fails badly. Why? A: Most likely wire-load-model-based synthesis underestimated interconnect delay and congestion; use physically-aware/topographical synthesis with a floorplan, and check clock uncertainty and derates.
• Q: Why can an if-else chain be slower than a case statement? A: if-else infers priority logic — a serial chain of muxes whose depth grows with the number of conditions — while a parallel case infers one mux level when the conditions are mutually exclusive.
• Q: What causes an unintended latch and how do you detect it? A: An incompletely assigned combinational block (missing else or default); it shows up as latch inference warnings in the synthesis log and as latch cells in the netlist report.
• Q: Reducing frequency halves the power — does it halve the battery drain? A: No. At the same voltage the task simply takes twice as long, so energy per operation is unchanged; only lowering V_DD (or doing less work) reduces energy.
• Q: Why is synthesis run at the slow corner but leakage checked at the fast/hot corner? A: Setup paths are worst when cells are slow (SS, low V, high T), while leakage current is highest when transistors are fast and hot (FF, high V, 125 °C).

Common mistakes

• Writing P = C·V²·f and forgetting the activity factor α, or using α = 1 for ordinary data nets instead of ~0.1–0.2.
• Claiming clock gating or DVFS reduces leakage, or claiming power gating has no state and latency cost.
• Assuming lowering frequency saves energy per operation — it saves power only.
• Leaving incomplete case/if statements, mixing blocking and non-blocking assignments in one block, or hand-coding gated clocks instead of letting the tool insert ICG cells.
• Over-constraining or papering over paths with set_false_path/set_max_delay so reports look clean while real violations survive to silicon.
• Skipping formal equivalence after synthesis or after a manual netlist ECO.
• Forgetting a level shifter at a low-to-high voltage crossing, or forgetting that isolation/retention logic and the switch-enable network must themselves be always-on.
• Trusting wire-load-model synthesis numbers as final, and quoting dynamic power from the slow corner without a matching activity file (SAIF/VCD).

Related topics

Static timing analysis · CMOS digital IC design · VLSI design flow · Design verification and UVM basics · SoC design: AMBA buses and IP integration · Physical design and place-and-route.