SoC design: AMBA buses and IP integration

In short

A System-on-Chip (SoC) puts processors, memories, accelerators and peripherals on one die, and they talk through an on-chip interconnect. AMBA (Advanced Microcontroller Bus Architecture), an open ARM specification, defines the socket - AHB, APB, AXI, ACE, AXI-Stream - that every reusable IP block presents, so blocks from different vendors can be stitched together. IP integration is the engineering of that stitching: memory maps, arbitration, clock and reset domains, power domains, and verification of protocol compliance. It is examined in VLSI/SoC design and digital system design papers (GATE EC/CS touches bus concepts, handshakes and FSMs), and it is the single most asked area in front-end interviews at Qualcomm, Intel, NVIDIA, AMD, Texas Instruments, Samsung, Broadcom, Microchip, Nordic, Arm India, Bosch, Wipro/LTTS/Sasken and C-DAC, plus India's SHAKTI and VEGA processor programmes.

Explained

SoC anatomy and the role of the interconnect

• A typical SoC has a CPU cluster (Arm Cortex-A/M or RISC-V such as SHAKTI/VEGA), memory controller (LPDDR), on-chip SRAM/ROM, DMA, accelerators (GPU, ISP, NPU), peripherals (UART, SPI, I2C, GPIO, timers, watchdog), interrupt controller, clock/reset/power management unit and debug/trace.
• Masters (managers) initiate transactions: CPU, DMA, GPU. Slaves (subordinates) respond: memories, peripheral registers. AMBA 5 renamed master/slave to manager/subordinate; both terms appear in interviews.
• The interconnect routes a transaction by address decoding (which subordinate), arbitration (which manager wins), and response routing back to the originator.
• Design intent split: high-bandwidth traffic (CPU↔DRAM, display, NPU) goes on AXI/ACE; low-bandwidth register traffic goes on APB behind a bridge, so slow peripherals never stall the fast fabric.
• Topologies: shared bus (one transaction at a time, cheap) → crossbar/matrix (parallel paths, area grows as M×N) → NoC (packet-switched routers, used above roughly 20-30 masters, e.g. Arteris/NetSpeed-style fabrics).

AMBA family and generations

• ASB/APB (AMBA 1, 1996) → AHB (AMBA 2, 1999) → AHB-Lite, Multi-layer AHB, APB3 (AMBA 3, 2003) with AXI3 → AMBA 4 (2010): AXI4, AXI4-Lite, AXI4-Stream, ACE, ACE-Lite → AMBA 5 (2013 onward): CHI (coherent hub interface), AHB5, APB5, AXI5.
• APB - simple, non-pipelined, low power, two-cycle minimum transfer, single 32-bit transfer only, no bursts. Signals: PSEL, PENABLE, PADDR, PWRITE, PWDATA, PRDATA, PREADY, PSLVERR (PREADY/PSLVERR from APB3; PPROT/PWAKEUP in APB4/5).
• AHB / AHB-Lite - pipelined (address phase of transfer N overlaps data phase of N−1), single outstanding transaction, bursts up to 16 beats, split/retry responses in full AHB (dropped in AHB-Lite, which also allows only one master). Signals: HADDR, HTRANS, HWRITE, HSIZE, HBURST, HWDATA, HRDATA, HREADY, HRESP, HPROT, HMASTLOCK.
• AXI (AMBA 3/4) - five independent channels, burst-based, multiple outstanding and out-of-order transactions, separate read and write data paths (full duplex).
• AXI4-Lite - single-beat, no bursts, no IDs; used for control registers. AXI4-Stream - no addresses at all, pure data flow (TDATA, TVALID, TREADY, TLAST, TKEEP, TUSER) for DSP/video pipelines.
• ACE / ACE-Lite - adds hardware cache coherency: snoop address, snoop data and snoop response channels plus ARDOMAIN/ARSNOOP/ARBAR signals. CHI replaces the channel-wire model with a packet/credit-based layered protocol for many-core servers.

AXI in detail (the heavily examined part)

• Five channels, each with its own VALID/READY pair: Write Address (AW), Write Data (W), Write Response (B), Read Address (AR), Read Data (R). Address/control is decoupled from data, so a manager can issue addresses ahead of data.
• Handshake rule: transfer occurs on the rising edge where VALID and READY are both high. VALID must not wait for READY; once asserted, VALID and payload must remain stable until the handshake. READY may be asserted before, with or after VALID, and may be withdrawn if no handshake happened. Mutual waiting is the classic deadlock.
• Burst signals: AxADDR (start address), AxLEN (beats − 1; 1-16 in AXI3, 1-256 for INCR in AXI4), AxSIZE (bytes per beat = 2^AxSIZE), AxBURST (00 FIXED, 01 INCR, 10 WRAP), AxCACHE, AxPROT, AxLOCK, AxQOS, AxREGION, AxUSER.
• Rules: a burst must not cross a 4 KB address boundary (so an interconnect never has to re-decode mid-burst); WRAP requires a burst length of 2, 4, 8 or 16 beats (AxLEN = 1, 3, 7 or 15) and a start address aligned to the size of each beat (2^AxSIZE), the address wrapping at the total-transfer-size boundary; FIXED is for repeated access to one location such as a FIFO port.
• Byte lanes and strobes: WSTRB has one bit per data byte lane; narrow and unaligned transfers are expressed purely by strobes. Read data needs no strobes.
• Write response is per burst (one BVALID per write burst); read response is per beat (RRESP on each RDATA beat, with RLAST on the final beat). Responses: 00 OKAY, 01 EXOKAY (exclusive access), 10 SLVERR (subordinate detected an error), 11 DECERR (interconnect found no subordinate at that address).
• IDs and ordering: AxID tags transactions. Same ID ⇒ responses must return in order; different IDs ⇒ may complete out of order, which is how a fast SRAM response overtakes a slow DRAM one. The interconnect appends manager-number bits to the ID and strips them on return.
• Outstanding transactions = addresses issued but not yet completed; more outstanding capability hides memory latency. Interleaving of write data from different IDs was allowed in AXI3 (WID) and removed in AXI4.
• Atomic access: AXI uses exclusive (LOCK=01, with EXOKAY) and locked (AXI3 only) accesses; AXI4 dropped locked transfers. Arm's LDREX/STREX and RISC-V LR/SC map onto exclusive monitors.
• Low-power interface: CSYSREQ/CSYSACK/CACTIVE handshake lets a clock controller ask a peripheral if its clock may be removed. AXI5/APB5 add wake-up signalling (AWAKEUP).
• Reset: ARESETn is active-low asynchronous assert / synchronous de-assert; during reset all VALID signals must be driven low, and a manager must wait at least one clock after reset de-assertion before asserting VALID.

Arbitration, QoS and performance

• Arbitration schemes: fixed priority (simple, starves low priority), round-robin (fair), weighted round-robin / least-recently-used, TDMA, and QoS-regulated arbitration using AxQOS plus bandwidth/latency regulators in the interconnect.
• Starvation and priority inversion are real risks; display and camera traffic is usually given a latency-critical class because a frame-buffer underrun is visible.
• Throughput = data bus width × clock frequency × efficiency. Efficiency falls with short bursts (address overhead), narrow transfers, 4 KB boundary splits, width converters, and insufficient outstanding depth.
• Little's law view: required outstanding beats ≈ bandwidth × round-trip latency / bytes per beat - the standard way to size an AXI port's outstanding depth.
• Register slices (pipeline stages inserted on channels) fix timing at the cost of latency; width converters, clock converters, protocol converters (AXI↔AHB↔APB bridges) are standard interconnect blocks.

IP integration: steps, deliverables and hazards

1. Specification and memory map: fix the address map (base + size per subordinate, non-overlapping, naturally aligned), register map (offset, width, access type, reset value), interrupt map and clock/reset/power domains. Captured machine-readably in IP-XACT (IEEE 1685) and SystemRDL, which generate RTL, headers and documentation.
2. IP selection: *soft IP* (synthesisable RTL - portable, tunable), *firm IP* (gate-level netlist) and *hard IP* (GDSII macro - PLL, SRAM, PHY, ADC; fixed performance, foundry-specific). Sources: Arm, Synopsys DesignWare, Cadence, Rambus, plus in-house and open-source (SHAKTI, VEGA, OpenTitan).
3. Integration/stitching: instantiate IPs, connect to interconnect, tie off unused inputs correctly, add glue (bridges, CDC, synchronisers, level shifters, isolation cells). Mostly generated by scripts/IP-XACT rather than hand-written, to avoid connection bugs.
4. Clock domain crossing: two-flop synchronisers for single-bit control, asynchronous FIFOs or handshake for data buses, Gray coding for pointers; never synchronise a multi-bit bus bit-by-bit.
5. Reset strategy: asynchronous assert, synchronous de-assert through a reset synchroniser per clock domain; order resets so configuration survives.
6. Power intent: described in UPF (IEEE 1801) - power domains, switches, retention, isolation and level shifters for multi-voltage and power-gated IP.
7. Verification: protocol checkers/assertions (ARM AMBA VIP, Synopsys/Cadence/Siemens VIP, open-source SVA packs), register tests generated from the register map, connectivity and interrupt tests, performance/traffic-profile tests, and formal protocol compliance.
8. Sign-off deliverables: RTL + testbench, synthesis and timing constraints (SDC), Liberty/LEF/GDS for hard IP, UPF, IP-XACT, integration guide, firmware driver.
9. Legal/commercial in India: IP is licensed (per-use or royalty-bearing) and protected as copyright in source code plus patents; licence terms, export-control obligations and NDAs bind the integrator. India's Semiconductor Mission (ISM), the Design Linked Incentive (DLI) scheme and C-DAC/Chips to Startup (C2S) fund fabless SoC design; the SCL Mohali foundry and new fabs (Dholera, Assam) are the domestic manufacturing route. Scheme details and incentive percentages change - check the current MeitY notification rather than relying on a remembered figure.

Comparison and choosing a protocol

Key points

• AMBA - open ARM on-chip interconnect specification family: APB, AHB, AXI, ACE, CHI, AXI-Stream.
• Manager/subordinate - AMBA 5 names for master/slave; the manager starts the transaction.
• APB - non-pipelined, no bursts, two-cycle minimum, PREADY for wait states; cheapest for registers.
• AHB-Lite - pipelined single-master bus, one outstanding transfer, HREADY stalls the whole bus.
• AXI five channels - AW, W, B, AR, R; each has VALID/READY and flows independently.
• Handshake rule - VALID must never wait for READY; payload stays stable until both are high on a clock edge.
• AxLEN = beats − 1 - 1-16 beats in AXI3, up to 256 beats for INCR in AXI4.
• AxSIZE - bytes per beat = 2^AxSIZE, must not exceed the data bus width.
• Burst types - FIXED (same address, FIFO), INCR (normal memory), WRAP (cache line fill, power-of-two length, aligned).
• 4 KB rule - no AXI burst may cross a 4 KB boundary; the interconnect splits such accesses.
• WSTRB - per-byte write enable; the only mechanism for narrow or unaligned writes.
• Responses - OKAY, EXOKAY, SLVERR (subordinate error), DECERR (no subordinate decoded).
• Transaction ID - same ID means ordered completion; different IDs allow out-of-order and overtaking.
• Outstanding depth - must cover bandwidth × latency, else the port idles waiting for responses.
• IP types - soft (RTL), firm (netlist), hard (GDSII macro: PLL, SRAM, PHY).
• Integration standards - IP-XACT/IEEE 1685 for metadata and stitching, UPF/IEEE 1801 for power intent, SDC for constraints.
• CDC and reset - two-flop synchroniser for control, async FIFO for data, async-assert/sync-de-assert resets per domain.
• Low-power interface - CSYSREQ/CSYSACK/CACTIVE allow safe clock removal; AXI5/APB5 add wake-up signals.

Formulas and examples

Example 1 - AXI burst geometry and the 4 KB rule. A manager on a 64-bit (8-byte) AXI bus issues AWADDR = 0x0000_0FC0, AWLEN = 0x0F, AWSIZE = 3, AWBURST = INCR.

• Beats = 15 + 1 = 16; bytes per beat = 2³ = 8; burst bytes = 16 × 8 = 128.
• Address range = 0x0FC0 to 0x0FC0 + 127 = 0x103F. The 4 KB boundary is at 0x1000, so the burst crosses it - illegal.
• Largest legal burst from 0x0FC0 = 0x1000 − 0x0FC0 = 64 bytes = 8 beats (AWLEN = 7). The interconnect would otherwise split it into 8 + 8 beats.

Example 2 - Peak bandwidth and efficiency. A 128-bit AXI4 port runs at 500 MHz.

• Width = 128/8 = 16 bytes → BW = 16 × 500 × 10⁶ = 8 × 10⁹ = 8 GB/s.
• A 16-beat INCR burst moves 256 bytes. If each burst needs 1 cycle for the address and 16 data cycles with 3 idle cycles between bursts: cycles = 1 + 16 + 3 = 20 → η = 16/20 = 80% → effective 6.4 GB/s.
• Replace with 4-beat bursts (same 3 idle cycles): cycles = 1 + 4 + 3 = 8 → η = 4/8 = 50% → 4 GB/s. Longer bursts amortise overhead.

Example 3 - Outstanding transactions needed to hide DRAM latency. A video engine must sustain 2 GB/s from LPDDR with 150 ns read round-trip latency, using 64-byte read bursts.

• Data in flight = 2 × 10⁹ × 150 × 10⁻⁹ = 300 bytes.
• N ≥ 300/64 = 4.69 → 5 outstanding reads minimum; designers size it to 8 for margin and jitter.
• If the port supports only 2 outstanding reads, achievable BW = 2 × 64/150 ns = 128/1.5 × 10⁻⁷ ≈ 0.85 GB/s - well short, so the fix is more outstanding capability, not a wider bus.

Example 4 - APB versus AHB register access cost. A CPU writes 8 configuration registers. APB bridge adds 2 wait states per access; the AHB side needs 1 cycle per transfer.

• APB: (2 + 2) = 4 cycles each → 8 × 4 = 32 cycles on the APB clock.
• If APB runs at half the AHB clock, that is 64 AHB cycles, plus bridge latency - which is why boot-time register programming is often moved to a DMA or kept off the critical path.
• The same 8 words as one AHB 8-beat burst to memory ≈ 1 + 8 = 9 cycles: bursts cannot be used for scattered register writes, only for contiguous addresses.

Example 5 - Memory map decode.

• An access to 0x6000_0000 matches nothing → the interconnect returns DECERR, not a hang; a missing default subordinate is what causes bus lock-ups.

// AXI4-Lite write handshake in a subordinate (single register), illustrative
always @(posedge aclk) begin
  if (!aresetn) begin
    awready <= 1'b0; wready <= 1'b0; bvalid <= 1'b0; ctrl <= 32'b0;
  end else begin
    awready <= !awready && awvalid && !bvalid;      // one-cycle accept
    wready  <= !wready  && wvalid  && !bvalid;
    if (wready && wvalid && awready && awvalid) begin
      ctrl   <= wdata;                              // ignore WSTRB only if spec allows
      bvalid <= 1'b1; bresp <= 2'b00;               // OKAY
    end else if (bvalid && bready) begin
      bvalid <= 1'b0;                               // response consumed
    end
  end
end

Where it is used

• Mobile and consumer SoC teams: Qualcomm (Bengaluru/Hyderabad), Samsung SRI-B, MediaTek, Apple and Intel India build AXI/ACE/CHI fabrics for application processors and modems.
• Microcontrollers and automotive: NXP, Microchip, TI, Renesas, Bosch and Infineon use AHB-Lite/APB cores for Cortex-M-class MCUs in BLDC drives, instrument clusters and ADAS ECUs.
• FPGA and prototyping work: AMD-Xilinx Vivado IP Integrator and Intel Platform Designer connect everything over AXI4/AXI4-Lite/AXI-Stream - the usual first hands-on exposure in Indian labs and internships.
• Indian processor programmes: SHAKTI (IIT Madras) and VEGA (C-DAC) SoCs integrate RISC-V cores with AXI/AHB/APB peripheral subsystems; ISM/DLI-funded fabless startups (Mindgrove, InCore, Netrasemi, Saankhya) do exactly this work.
• Job roles: SoC integration engineer, RTL design engineer, interconnect/performance architect, design verification engineer (AMBA VIP), post-silicon validation, and IP/library engineer at Synopsys, Cadence and Siemens EDA India.
• Non-ARM analogues worth knowing: Wishbone and TileLink in open-source RISC-V SoCs, and OCP - the same integration concepts, different signal names.

Interview questions

• Q: Why does AXI use five independent channels? A: Decoupling address, data and response lets reads and writes proceed simultaneously, allows multiple outstanding transactions, and lets each channel be pipelined or back-pressured independently for higher throughput.
• Q: State the AXI handshake rule and the deadlock it prevents. A: A transfer happens when VALID and READY are both high on a rising clock edge; VALID must not be held back waiting for READY. If both sides waited for the other, the channel would deadlock.
• Q: Why must an AXI burst not cross a 4 KB boundary? A: 4 KB is the smallest page/decode granularity assumed, so the interconnect can decode the destination once from the start address without re-decoding mid-burst or splitting across two subordinates.
• Q: What is the difference between AxLEN and the number of beats? A: AxLEN is beats − 1; AxLEN = 0 means one beat, and AXI4 allows AxLEN up to 255 (256 beats) for INCR bursts.
• Q: When would you use a WRAP burst? A: For cache line fills starting at the critical word - the address wraps back to the line start; length must be 2, 4, 8 or 16 and the start address aligned to the transfer size.
• Q: How does AXI support out-of-order completion? A: Transactions carry AxID; those with different IDs may complete in any order, while transactions with the same ID must return in order. The interconnect widens the ID with manager bits to keep them unique.
• Q: Difference between SLVERR and DECERR? A: SLVERR means a decoded subordinate was reached but reported an error (bad register, unsupported size); DECERR means the interconnect found no subordinate at that address.
• Q: Why keep slow peripherals on APB behind a bridge instead of on AXI? A: APB is tiny and simple, needs no burst or outstanding logic, and its wait states do not stall the high-performance fabric; register traffic needs no bandwidth.
• Q: AHB-Lite versus full AHB? A: AHB-Lite removes multi-master arbitration and the SPLIT/RETRY responses, assuming a single master - far simpler, which suits a microcontroller with an external bus matrix.
• Q: What does ACE add over AXI4? A: Hardware cache-coherency support - snoop address, snoop data and snoop response channels, cache-state signalling and barriers - so caches in different clusters stay coherent; ACE-Lite gives one-way coherency for IO masters.
• Q: Your AXI master has 8 GB/s of wire bandwidth but delivers 2 GB/s. What do you check? A: Outstanding depth against latency, burst length, 4 KB splits, width/clock converters, interconnect arbitration priority and whether the subordinate is throttling READY.
• Q: How do you cross a 32-bit AXI data path between two asynchronous clock domains? A: Use an asynchronous FIFO (or a vendor AXI clock converter) per channel with Gray-coded pointers and two-flop synchronisers on the control/pointer bits - never synchronise the data bits individually.
• Q: What is IP-XACT used for? A: IEEE 1685 XML describing an IP's ports, bus interfaces, registers and memory map, so integration tools generate the stitching RTL, headers and documentation instead of hand-coding them.

Common mistakes

• Treating AxLEN as the beat count instead of beats − 1, and then miscomputing burst bytes.
• Making VALID depend on READY (or vice versa) in RTL - a protocol violation that deadlocks in simulation and silicon.
• Forgetting WSTRB for narrow/unaligned writes, or driving strobes outside the addressed byte lanes.
• Issuing one BVALID per write beat; the write response is one per burst, while read responses come per beat.
• Assuming a wider bus fixes a bandwidth shortfall when the real limit is outstanding depth or latency.
• Overlapping or misaligned memory-map regions, and leaving no default subordinate - so a stray address hangs the bus instead of returning DECERR.
• Synchronising a multi-bit bus with per-bit two-flop synchronisers, or forgetting reset synchronisers per clock domain.
• Reusing an AHB/APB mental model on AXI - expecting a single shared bus, in-order responses and a global HREADY-style stall.

Related topics

• VLSI design flow · Design verification and UVM basics · Static timing analysis · Logic synthesis and low-power design · Computer architecture: caches and memory hierarchy · FPGA-based prototyping and embedded interfaces