BJT and MOSFET

In short

The bipolar junction transistor (BJT) and the metal-oxide-semiconductor field-effect transistor (MOSFET) are the two three-terminal devices on which all analog and digital electronics is built. A BJT is a current-controlled device in which a small base current controls a large collector current; a MOSFET is a voltage-controlled device in which the gate-source voltage controls the channel current through an insulating oxide. Every amplifier, switch, logic gate, SMPS, motor drive and VLSI chip reduces to one of these two, so the topic carries the largest single share of marks in GATE EC/IN, ESE, ISRO, DRDO and BARC papers and is the standard opening round in placement interviews at Texas Instruments, Analog Devices, Qualcomm, Intel, NXP, Bosch, Cadence, Synopsys, Tata Elxsi and Tejas Networks. It is examined as device physics (structure, regions, characteristics), as DC analysis (Q-point, load line) and as a switch (saturation, conduction loss).

Explained

BJT: structure, operation and regions

• Three doped regions — emitter (heavily doped), base (very thin and lightly doped), collector (moderately doped, largest area) — giving two junctions: emitter-base (EB) and collector-base (CB). Two polarities: NPN (electrons are the majority carriers injected, faster, preferred) and PNP.
• The device is not symmetric: swapping emitter and collector gives a very low β (reverse-active mode), because doping levels and areas differ.
• Normal (forward-active) operation of an NPN: EB forward biased (V_BE ≈ 0.7 V), CB reverse biased. Electrons injected from emitter into the thin base mostly diffuse across before recombining and are swept into the collector by the CB depletion field. Only a small fraction recombines in the base — that fraction is the base current.
• Current relations: I_E = I_B + I_C (KCL), I_C = αI_E, I_C = βI_B, with α = common-base current gain (0.95-0.998) and β = h_FE = common-emitter current gain (20-500).
• Four regions of operation:

• Ebers-Moll / transport model: I_C ≈ I_S·exp(V_BE/V_T) in the active region — the collector current is set by V_BE *exponentially*, and is almost independent of V_CE. β is a consequence, not the cause.
• Leakage: I_CBO is CB leakage with the emitter open; in CE configuration it is amplified: I_CEO = (1+β)I_CBO. It roughly doubles every 10 °C rise, which is the root of thermal instability.

BJT: configurations, characteristics and second-order effects

• Input characteristic (CE): I_B versus V_BE looks like a forward-biased diode curve; the curve shifts right as V_CE increases, because base-width narrowing lowers I_B for a given V_BE.
• Output characteristic (CE): I_C versus V_CE for fixed I_B — a steep rise below V_CE ≈ 0.2-0.3 V (saturation), then a nearly flat active region with a slight upward slope.
• Early effect (base-width modulation): increasing V_CE widens the CB depletion region, narrows the effective base, reduces recombination, so β and I_C rise slightly. Extrapolating the flat portions backwards meets the voltage axis at −V_A (Early voltage, 20-500 V); it gives finite output resistance r_o = V_A/I_C.
• Other limits: punch-through (base fully depleted at high V_CE, junctions merge), avalanche breakdown with BV_CBO > BV_CER > BV_CEO, secondary breakdown (local current crowding and a hot spot destroying the die), and thermal runaway — I_C rises with temperature, dissipation rises, temperature rises further. Emitter degeneration (R_E) and heat sinking are the cures.
• β varies with I_C (falls at very low and very high current), with temperature (rises roughly 0.5-1% per °C) and from device to device by 2-3×, so no good design depends on the exact value of β.
• V_BE has a temperature coefficient of about −2 mV/°C at constant I_C — used deliberately in bandgap references and V_BE-based temperature sensors.

BJT biasing, DC load line and the transistor as a switch

• Purpose of biasing: place the quiescent point (Q-point) in the middle of the active region so the signal swings without clipping, and keep it there despite β spread and temperature.
• Fixed bias (base resistor only): simple but Q-point is directly proportional to β — poor stability (stability factor S ≈ 1+β).
• Collector-to-base feedback bias: some negative feedback, moderate stability.
• Emitter bias / voltage-divider (self) bias: R1-R2 divider sets V_B, R_E sets I_E ≈ (V_B − V_BE)/R_E — nearly independent of β. This is the standard exam circuit.
• Stability factor S = ∂I_C/∂I_CO; smaller is better. For voltage-divider bias S = (1+β)(R_TH+R_E)/(R_TH+R_E+βR_E).
• DC load line: the line I_C = (V_CC − V_CE)/(R_C+R_E) drawn on the output characteristics; intercepts are V_CE = V_CC (cut-off) and I_C = V_CC/(R_C+R_E) (saturation). The AC load line is steeper because the emitter bypass capacitor shorts R_E at signal frequencies.
• As a switch: drive the base hard so that I_B > I_C(sat)/β. The ratio I_B(actual)/I_B(min) is the overdrive factor; forced β is lower than the data-sheet β. Saturation gives low loss but storage time on turn-off (excess base charge) — avoided by a Schottky clamp or by not driving fully into saturation.

MOSFET: structure, threshold and operation

• Structure of an n-channel enhancement MOSFET: p-type substrate (body), two heavily doped n⁺ source and drain regions, and a gate electrode (originally metal, heavily doped polysilicon in classic CMOS, metal again in modern high-k/metal-gate nodes) over a thin SiO₂ gate oxide. The gate draws essentially no DC current — it is a capacitor plate.
• Threshold voltage V_T (V_th): the V_GS at which the surface under the gate inverts to n-type and a continuous channel forms. Typically 0.3-1 V in ICs, 2-4 V in power MOSFETs (logic-level types ~1-2 V).
• Overdrive voltage V_OV = V_GS − V_T. For V_GS < V_T the device is nominally OFF (subthreshold region).
• Triode / linear / ohmic region (V_DS < V_OV): the channel exists along the full length; the device behaves like a voltage-controlled resistor at small V_DS. The channel is thinner at the drain end because V_GD is smaller.
• Pinch-off and saturation (V_DS ≥ V_OV): the channel just vanishes at the drain end; further increase in V_DS extends the pinch-off point slightly but does not increase current much — I_D becomes almost constant and is set by V_GS. (Note the wording trap: in a BJT "saturation" means fully ON/low voltage, in a MOSFET "saturation" means constant-current/amplifier region.)
• Body/substrate terminal: usually tied to the source. In ICs where it cannot be, a reverse V_SB raises V_T — the body effect, V_T = V_T0 + γ(√(2φ_F+V_SB) − √(2φ_F)).
• Subthreshold conduction: I_D falls exponentially below V_T with a slope limited to about 60 mV/decade at 300 K (2.3kT/q); this floor is why supply voltages cannot scale indefinitely, and it sets standby leakage in CMOS chips.

MOSFET types, characteristics and second-order effects

• Four types: n-channel and p-channel, each enhancement (normally OFF, needs |V_GS| > |V_T| to conduct) or depletion (channel implanted at manufacture, conducts at V_GS = 0, turned off by reverse gate bias). Enhancement NMOS and PMOS together form CMOS.
• For PMOS all polarities reverse: V_GS, V_T and V_DS are negative and current flows from source to drain.
• Transfer characteristic (I_D vs V_GS) is a square law in saturation — contrast the BJT's exponential. Output characteristic (I_D vs V_DS) shows the triode region, the knee at V_DS = V_OV, and a slightly rising saturation region.
• Channel-length modulation: the slope in saturation, modelled by (1 + λV_DS); r_o = 1/(λI_D) ≈ V_A/I_D. Short-channel devices have large λ, hence low gain.
• Other short-channel effects: velocity saturation (current becomes closer to linear in V_OV), drain-induced barrier lowering (V_T falls with V_DS), hot-carrier degradation, gate-oxide tunnelling leakage. These drove the move to FinFET and gate-all-around structures.
• Capacitances C_GS, C_GD (Miller), C_DB limit speed; unity-gain frequency f_T = g_m/[2π(C_GS+C_GD)]. Gate charge Q_g, not gate current, sets the switching drive requirement in power circuits.
• Power MOSFETs are vertical (VDMOS/trench) devices with an intrinsic body diode from source to drain — useful for freewheeling in inverters, but slow in reverse recovery. Key ratings: V_DSS, I_D, R_DS(on), Q_g, and SOA.
• R_DS(on) has a positive temperature coefficient, so paralleled MOSFETs share current naturally and there is no second breakdown — the main reason MOSFETs replaced BJTs in switching power supplies and motor drives. The IGBT combines a MOSFET gate with a bipolar output for high-voltage, high-current use.
• MOSFET gates are destroyed by ESD (SiO₂ breaks down at about 1 V per nanometre of oxide); handle with wrist straps, conductive foam and ESD-safe benches, and keep gate-source pull-down resistors in circuits. Internal gate-protection Zeners are present in some discrete power parts, but must not be assumed.

Small-signal parameters and BJT versus MOSFET

• Both devices, biased in their constant-current region, become a transconductance g_m with an output resistance r_o; the BJT additionally has a finite input resistance r_π because the base takes current.
• Intrinsic gain g_m·r_o is V_A/V_T for a BJT (typically 1,000-5,000, independent of current) and 2V_A/V_OV for a MOSFET (typically 20-100) — the BJT wins on gain per stage.

• Indian standards and practice: discrete numbering follows JEDEC (2N2222, 2N3055), Pro-Electron (BC547, BD139), JIS (2SC…) and manufacturers' own codes (IRF540N) rather than a separate BIS part series; finished electronic equipment sold in India needs BIS registration under the Electronics and IT Goods (Compulsory Registration) Order, and semiconductor manufacturing and ATMP investment is governed by the India Semiconductor Mission (ISM) schemes — SCL Mohali, the Tata-PSMC fab at Dholera and Micron's Sanand assembly plant are the current flagship sites. Exact incentive terms change, so check the latest MeitY notification.

Key points

• BJT - current-controlled, bipolar, three regions used: cut-off (OFF), active (amplifier), saturation (ON).
• α and β - α = I_C/I_E, β = I_C/I_B, β = α/(1−α), α = β/(1+β); I_E = I_B + I_C always.
• Active region - EB forward, CB reverse; I_C set exponentially by V_BE and nearly independent of V_CE.
• I_CEO = (1+β)I_CBO - leakage is β-multiplied in CE, doubling about every 10 °C.
• Early effect - V_CE narrows the base, so I_C rises slightly; gives r_o = V_A/I_C.
• V_BE drift - about −2 mV/°C; β rises with temperature; both destabilise the Q-point.
• Voltage-divider bias - β-independent Q-point because R_E fixes I_E; the standard stable bias.
• Load line - intercepts V_CC and V_CC/(R_C+R_E); Q-point near mid-line for maximum symmetric swing.
• BJT switch - must satisfy I_B > I_C(sat)/β; overdrive gives low V_CE(sat) but adds storage time.
• MOSFET - voltage-controlled, unipolar, insulated gate, zero DC gate current.
• V_T and V_OV - channel forms at V_GS = V_T; V_OV = V_GS − V_T decides the region and the current.
• Region boundary - V_DS < V_OV triode (resistive); V_DS ≥ V_OV saturation (constant current, used for amplification).
• Square law - I_D = ½µ_nC_ox(W/L)V_OV² in saturation, against the BJT's exponential.
• Channel-length modulation - factor (1+λV_DS); r_o = 1/(λI_D).
• Body effect - reverse source-body bias raises V_T; adds a second transconductance g_mb = χg_m.
• Subthreshold slope - best case ≈ 60 mV/decade at room temperature; sets CMOS leakage.
• R_DS(on) - positive temperature coefficient, so no thermal runaway and easy paralleling; power MOSFETs include a body diode.
• "Saturation" is opposite - fully-ON low-voltage state in a BJT, constant-current amplifying state in a MOSFET.

Formulas and examples

Example 1 — BJT currents and leakage. A transistor has β = 100 and I_B = 20 µA.

• α = 100/101 = 0.990.
• I_C = 100 × 20 µA = 2.00 mA; I_E = 2.00 + 0.02 = 2.02 mA.
• If I_CBO = 50 nA, then I_CEO = 101 × 50 nA = 5.05 µA — 100× larger, which is why CE leakage matters.

Example 2 — Voltage-divider bias, Q-point and small-signal parameters. V_CC = 12 V, R1 = 47 kΩ, R2 = 10 kΩ, R_C = 2.2 kΩ, R_E = 1 kΩ, β = 150, V_BE = 0.7 V.

1. V_TH = 12 × 10/57 = 2.105 V; R_TH = 47×10/57 = 8.246 kΩ.
2. I_B = (2.105 − 0.7)/(8.246k + 151 × 1k) = 1.405/159.25k = 8.82 µA.
3. I_C = 150 × 8.82 µA = 1.323 mA; I_E = 151 × 8.82 µA = 1.332 mA.
4. V_CE = 12 − (1.323 × 2.2) − (1.332 × 1) = 12 − 2.912 − 1.332 = 7.76 V → safely in the active region.
5. g_m = 1.323 mA/26 mV = 50.9 mA/V; r_π = 150/50.9 mA/V = 2.95 kΩ; with V_A = 100 V, r_o = 100/1.323 mA = 75.6 kΩ; intrinsic gain g_m r_o ≈ 3,850.
6. S = 151 × 9.246/159.246 = 8.77 — good stability (fixed bias would give S ≈ 151).

Example 3 — NMOS in both regions. k'_n = 200 µA/V², W/L = 10, V_T = 0.7 V, V_GS = 2 V, λ = 0.02 V⁻¹. So V_OV = 1.3 V and k'_n(W/L) = 2 mA/V².

• At V_DS = 3 V: 3 > 1.3, so saturation. I_D = ½ × 2m × 1.3² = ½ × 2m × 1.69 = 1.69 mA (1.79 mA including the (1+λV_DS) = 1.06 factor).
• g_m = 2 mA/V² × 1.3 V = 2.6 mA/V; r_o = 1/(0.02 × 1.69 mA) = 29.6 kΩ; intrinsic gain = 77 — far below the BJT's 3,850 at a similar current.
• At V_DS = 0.2 V: 0.2 < 1.3, so triode. I_D = 2m[(1.3 × 0.2) − (0.04/2)] = 2m[0.26 − 0.02] = 0.48 mA; effective resistance = 0.2/0.48 mA ≈ 417 Ω (the small-signal estimate 1/(2m × 1.3) = 385 Ω).

Example 4 — BJT as a switch. V_CC = 5 V, R_C = 1 kΩ, R_B = 10 kΩ, β(min) = 100, V_in = 5 V, V_BE = 0.7 V, V_CE(sat) = 0.2 V.

1. I_B = (5 − 0.7)/10 kΩ = 0.43 mA.
2. I_C(sat) = (5 − 0.2)/1 kΩ = 4.8 mA → I_B(min) = 4.8/100 = 48 µA.
3. 0.43 mA ≫ 48 µA, so the device is saturated; overdrive factor = 0.43/0.048 ≈ 9, forced β = 4.8/0.43 ≈ 11.
4. Dissipation in the transistor = 0.2 V × 4.8 mA ≈ 0.96 mW.

Example 5 — Power switch conduction loss, MOSFET versus BJT. A 10 A DC load at 24 V.

• MOSFET with R_DS(on) = 44 mΩ (typical for an IRF540N-class part at V_GS = 10 V; check the actual data sheet, as it rises roughly 1.5-2× at 125 °C): P = 10² × 0.044 = 4.4 W, drop = 0.44 V. Gate drive needs only charge, ≈ Q_g·V_GS·f_s in average power.
• BJT at V_CE(sat) = 0.5 V: P = 0.5 × 10 = 5.0 W, *plus* a continuous base current of about 10/20 = 0.5 A at 1 V ≈ 0.5 W of drive.
• With θ_JA = 62 °C/W (TO-220, no heat sink) the 4.4 W MOSFET would sit at 25 + 273 = 298 °C — impossible, so a heat sink giving θ_JA ≈ 5 °C/W is mandatory (25 + 22 = 47 °C). This is the standard exam point: conduction loss decides the heat sink, not the current rating.

Where it is used

• VLSI and semiconductor design: CMOS logic, SRAM, I/O drivers and analog IP at Intel, Qualcomm, AMD, NXP, Texas Instruments, Analog Devices, Micron and Synopsys/Cadence design centres in Bengaluru, Hyderabad, Noida and Pune; device/characterisation work at SCL Mohali and the new ISM-supported fab and ATMP units.
• Power electronics and drives: MOSFETs and IGBTs in SMPS, solar inverters and string optimisers, EV traction inverters and on-board chargers, BLDC fan and pump controllers — Tata Motors, Mahindra, Ather, Ola Electric, Delta, Luminous, Havells, Bosch, Kirloskar.
• Analog and instrumentation front-ends: BJTs for low-noise, well-matched, high-g_m stages (current mirrors, bandgap references, V_BE temperature sensors, audio output stages); MOSFETs for high-impedance sensor inputs and switched-capacitor circuits.
• Telecom and RF: RF BJTs/HBTs and LDMOS or GaN FETs in base-station and defence transmitter chains at Tejas Networks, BEL, DRDO labs and ISRO payload groups.
• Discrete and board-level design: BC547/2N2222 small-signal switching, TIP122 Darlington relay and solenoid drives, IRFZ44N/IRF540N load switches, level shifters and reverse-polarity protection in embedded products.
• Job roles: analog/mixed-signal design engineer, physical design and DFT engineer, device characterisation and reliability engineer, power electronics engineer, hardware design engineer, test and validation engineer.

Interview questions

• Q: Why is the base of a BJT made thin and lightly doped? A: So that most injected carriers diffuse across to the collector before recombining, which keeps the base current small and β high.
• Q: Why can't a BJT's emitter and collector be interchanged? A: The emitter is heavily doped and the collector is lightly doped with a larger area; reversing them gives a much lower current gain (reverse-active mode).
• Q: What exactly controls the collector current in the active region? A: V_BE controls it exponentially; I_C = βI_B is a consequence of the small recombination fraction in the base, and β itself varies with current and temperature.
• Q: What is the Early effect and why does it matter? A: Increasing V_CE narrows the effective base width, raising I_C slightly; it gives the transistor a finite output resistance r_o = V_A/I_C and so limits the gain of a single stage.
• Q: Why is "saturation" good in a BJT switch but a different thing in a MOSFET amplifier? A: BJT saturation is the fully-ON, low-V_CE state with both junctions forward biased; MOSFET saturation is the pinched-off constant-current region used for amplification.
• Q: Why is voltage-divider bias preferred over fixed bias? A: The emitter resistor sets I_E from (V_B − V_BE)/R_E, so the Q-point barely depends on β or on temperature-driven leakage; fixed bias has a stability factor of about 1+β.
• Q: Why do MOSFETs parallel easily in power circuits while BJTs do not? A: R_DS(on) rises with temperature, so a hotter MOSFET takes less current (self-balancing); a BJT's V_BE falls with temperature, so a hot device hogs current and runs away.
• Q: At the same bias current, which has higher transconductance and why? A: The BJT: g_m = I_C/V_T ≈ I_C/26 mV, while the MOSFET gives 2I_D/V_OV with V_OV typically a few hundred millivolts or more — often 5-10× lower.
• Q: What is the body effect and when does it bite? A: A reverse source-to-body bias raises V_T; it appears in stacked transistors and source followers in ICs where the source cannot be tied to the substrate.
• Q: Why is the subthreshold slope limited to about 60 mV/decade? A: It is set by thermal carrier statistics, 2.3kT/q at 300 K; this floor limits how far supply voltage and V_T can be scaled without leakage exploding.
• Q: A power MOSFET conducts in the reverse direction even when OFF — why? A: Its vertical structure contains an intrinsic body diode from source to drain, which conducts when the drain goes below the source.
• Q: Why do MOSFET gates need ESD precautions and a pull-down resistor? A: The thin gate oxide breaks down irreversibly at a few tens of volts, and a floating high-impedance gate can charge up and switch the device on unintentionally.

Common mistakes

• Writing I_E = I_C (ignoring I_B) in biasing problems, or using I_C where the question needs I_E through R_E.
• Not checking the region first: assuming active operation when the computed V_CE is below 0.2 V, or using the saturation MOSFET equation when V_DS < V_OV (and vice versa).
• Confusing BJT saturation (ON switch) with MOSFET saturation (constant-current amplifier region) — also confusing pinch-off with the channel being completely cut off.
• Designing with a single data-sheet β; it spreads 2-3× across parts and drifts with temperature, so the Q-point must be made β-independent.
• Forgetting the (1+β) multiplier when reflecting R_E into the base loop, and forgetting (1+β) on I_CBO.
• Treating a MOSFET gate as a true open circuit in switching design — it is a capacitor, and gate charge sets the drive current and switching loss.
• Sizing a power device from its current rating alone, without computing I²R_DS(on) or V_CE(sat)·I_C loss, θ_JA and the resulting junction temperature.

Related topics

FET amplifiers and biasing · Amplifiers and feedback · Semiconductor physics: energy bands, carriers and junctions · Semiconductor diodes and applications · Multistage and differential amplifiers · Power amplifiers