Data converters: ADC and DAC

Electronics and Communication Engineering (B.E./B.Tech) · Circuits and devices · free study notes for exams, placements and interviews

In short

A DAC converts an N-bit digital code into a proportional analog voltage or current; an ADC does the reverse, mapping a continuous analog signal into a finite set of digital codes. They are the interface between the physical world (sensors, microphones, antennas) and all digital processing, so every embedded system, instrument and radio contains them. In Indian university exams and GATE (EC/IN/EE) the standard questions are resolution and step size, quantisation noise and SNR, Nyquist/aliasing, the R-2R ladder, and comparison of flash, SAR, dual-slope and sigma-delta architectures. Placement interviews at Texas Instruments, Analog Devices, Cypress/Infineon, NXP, STMicroelectronics, Qualcomm, Bosch, ISRO/DRDO, BEL and Tata Elxsi routinely ask which converter you would pick for a given speed-accuracy-power target and why.

Explained

Fundamentals: resolution, step size, transfer characteristic

An N-bit converter has 2^N distinct codes and 2^N − 1 steps between the smallest and largest output.
Step size (LSB, resolution in volts) = V_FS / 2^N for a DAC, where V_FS is the full-scale reference. An 8-bit DAC with V_ref = 5 V has 1 LSB = 5/256 ≈ 19.53 mV.
Percentage resolution = (1/(2^N − 1)) × 100. For 8 bits ≈ 0.392%.
Full-scale output of a DAC = V_ref × (2^N − 1)/2^N — one LSB short of V_ref, because the all-ones code is the last step, not the reference itself.
Analog output V_o = V_ref × (b_{N-1}2^{N-1} + ... + b_0 2⁰)/2^N, i.e. V_ref × (decimal code)/2^N for a unipolar binary-weighted DAC.
An ADC's transfer curve is a staircase; a DAC's is a set of discrete points. Quantisation is irreversible — information inside one step is lost forever.
Codes: straight binary (unipolar), offset binary and two's complement (bipolar), BCD (in 3½-digit panel meters), Gray code (in some flash ADCs, to avoid large errors on comparator mis-decisions).
Monotonicity: a DAC is monotonic if the output never decreases as the code increases. Guaranteed if DNL error < 1 LSB. Essential in control loops, where non-monotonicity turns negative feedback into positive feedback.

Sampling, quantisation and noise

Sampling theorem (Nyquist–Shannon): a signal band-limited to f_m can be reconstructed exactly if f_s > 2f_m. The Nyquist rate is 2f_m; the Nyquist frequency is f_s/2.
Aliasing: components above f_s/2 fold back to |f − k·f_s| and masquerade as low frequencies; it cannot be removed afterwards. Prevented by an anti-aliasing low-pass filter ahead of the sample-and-hold.
Sample-and-hold (S/H): an analog switch plus hold capacitor plus buffer. It freezes the input so the ADC sees a constant value during conversion. Key specs: acquisition time, droop rate (I_leak/C), pedestal (hold step), feedthrough.
Aperture error: if the aperture (uncertainty) time is t_a, the maximum error on a sinusoid A sin(2πft) is ΔV = A·2πf·t_a. This is what limits high-frequency ADCs, not the comparator.
Quantisation error lies within ±Q/2 for a rounding quantiser (Q = step size), modelled as uniformly distributed noise of variance Q²/12, i.e. rms Q/√12.
Ideal SNR for a full-scale sine wave = 6.02N + 1.76 dB. Each extra bit buys about 6 dB.
ENOB (effective number of bits) = (SINAD − 1.76)/6.02 — the real resolution after noise and distortion, always less than N.
Dynamic specs: SINAD (signal to noise-and-distortion), THD, SFDR (spurious-free dynamic range), and for sigma-delta parts, dynamic range at a stated bandwidth.
Oversampling at K·f_s spreads the same quantisation noise over a wider band; filtering back to the signal band improves SNR by 10 log₁₀K dB, i.e. 3 dB (half a bit) per doubling. Noise shaping in a sigma-delta modulator does far better: an L-th order loop gains about (6L + 3) dB per doubling.
Companding (A-law, μ-law): non-uniform quantisation used in PCM telephony so that SNR stays roughly constant over a wide amplitude range; Indian/ITU-T E1 practice uses A-law, 8 bits at 8 kHz = 64 kbit/s per channel.

DAC architectures

Weighted-resistor (binary-weighted) DAC: each bit switches a resistor R, 2R, 4R ... 2^{N-1}R into an op-amp summing node. Simple; but needs a huge, precisely matched resistor spread (128:1 at 8 bits), so it is impractical beyond about 4-6 bits in ICs.
R-2R ladder DAC: uses only two resistor values in any number of bits — the workhorse. At every node the ladder looking right has impedance 2R, so each bit's contribution halves down the chain. Easy to trim and to integrate; the standard examination circuit.
- *Voltage-mode* R-2R: ladder driven from the bit switches to V_ref or ground, output taken at the top node.
- *Current-mode (inverted) ladder*: bit currents steered into a virtual ground, so node voltages do not swing — much faster, used in video DACs. Output V_o = −I·R_f.
Switched-current / current-steering DAC: an array of matched current sources (often unary MSBs + binary LSBs, "segmented"), summed into a load. Fastest class; used in RF transmitters and video.
String (Kelvin divider) DAC: 2^N series resistors with a 2^N-to-1 switch tree — inherently monotonic, but the component count doubles per bit; used for 6-10 bit trim DACs inside microcontrollers.
Multiplying DAC (MDAC): V_ref is an analog input, so output = code × V_in — used as a digitally programmable attenuator or gain block.
PWM / sigma-delta DAC: a 1-bit stream filtered by an RC or a switched-capacitor low-pass. Almost free in a microcontroller (timer + RC); low bandwidth, used for audio and for setting DC bias.
DAC specifications: resolution, settling time (to ±½ LSB), glitch impulse (worst at the major-carry transition 0111→1000), INL, DNL, offset and gain error, differential and integral nonlinearity, output compliance, latency.

ADC architectures

Flash (parallel) ADC: 2^N − 1 comparators on a resistor-string reference and a priority encoder. Fastest (GSPS) and lowest latency (one clock); comparator count, input capacitance, power and area all double per bit, so practical limit ≈ 6-8 bits. Used in oscilloscopes, radar front-ends, as sub-ADCs in pipelines.
Half-flash / two-step (subranging): a coarse flash, a DAC, a residue amplifier and a fine flash — 2·(2^{N/2} − 1) comparators instead of 2^N − 1. Big area saving for a small speed loss.
Pipeline ADC: cascade of low-resolution stages, each resolving a few bits and passing the amplified residue onwards, with digital delay alignment and redundancy (1.5-bit stages) for error correction. 8-16 bits at 10-500 MSPS; the standard choice for communications, imaging and software-defined radio.
Successive-approximation (SAR) ADC: a comparator, a DAC and SAR logic perform a binary search — MSB first, keep or discard, one bit per clock. N clocks per conversion, constant regardless of input. 8-18 bits, up to a few MSPS, very low power; built into almost every microcontroller (the ADC in an 8051 derivative, AVR, PIC, STM32 or Arduino is a SAR).
Counter (digital-ramp) ADC: a counter drives a DAC until it exceeds V_in. Simple, but conversion time varies with input, worst case 2^N clocks.
Tracking (servo) ADC: an up-down counter follows the input; very fast for slowly varying signals, slow to slew.
Integrating dual-slope ADC: integrates V_in for a fixed time T₁, then integrates the reference back to zero in T₂; the result depends only on the ratio T₂/T₁, so clock and capacitor drift cancel. Excellent noise rejection — making T₁ an integer multiple of 20 ms rejects 50 Hz mains interference and its harmonics, which is why Indian 3½- and 4½-digit multimeters and panel meters use it. Slow (a few to a few hundred conversions per second).
Charge-balancing / voltage-to-frequency converters: inherently integrating, good for isolated or noisy industrial transmitters.
Sigma-delta (ΔΣ) ADC: a 1-bit (or few-level) modulator oversampled far above Nyquist, with a loop filter that shapes quantisation noise out of the signal band, followed by a digital decimation filter. 16-24 bits at audio and instrumentation bandwidths; relaxes the anti-aliasing filter to a simple RC. Used in audio codecs, weigh-bridges, strain-gauge and energy-meter front-ends.
Comparison of speed-resolution trade-off: flash → pipeline → SAR → sigma-delta → dual-slope, in decreasing speed and generally increasing resolution.

Errors, testing and practical design

Offset error: the whole transfer curve shifted; the first code transition does not occur at ½ LSB.
Gain (full-scale) error: wrong slope after offset correction, expressed in % FS or LSB.
DNL (differential nonlinearity): deviation of each actual step from 1 LSB. DNL ≤ −1 LSB means a missing code in an ADC and non-monotonicity in a DAC.
INL (integral nonlinearity): deviation of the curve from a straight line (best-fit or endpoint), after removing offset and gain; it is the running sum of DNL.
Total unadjusted error (TUE): rss or worst-case sum of offset, gain, INL and quantisation — what actually matters in a measurement chain.
Latency vs throughput: a pipeline ADC outputs one sample per clock (high throughput) but each sample emerges several clocks later (latency) — a distinction interviewers like.
Reference matters more than the ADC: a 12-bit reading is only as good as V_ref's accuracy, drift (ppm/°C) and noise; a noisy 3.3 V rail used as reference wastes several bits.
Testing methods: histogram (code-density) test with a ramp or sine for DNL/INL, FFT test for SINAD/THD/SFDR, servo-loop test for code transition levels, beat-frequency test for dynamic behaviour.
Layout and system practice: separate analog and digital grounds joined at one point, decouple V_ref and AVDD, drive the ADC from a low-impedance buffer, allow for charge-kickback from the sampling capacitor, and keep the anti-aliasing filter ahead of the S/H. For isolated industrial inputs, use isolated sigma-delta modulators.
Standards and Indian practice: digital multimeters and panel instruments follow IEC 61010 (safety) and the accuracy statements of IEC/IS instrument standards; Indian smart energy meters (IS 16444 / IS 15959 for DLMS data exchange, BIS) use sigma-delta ADCs for current and voltage channels; telecom PCM follows ITU-T G.711 A-law and G.712. Figures in vendor data sheets vary by part — check the specific device.

Key points

Resolution - number of bits N; step size = V_FS/2^N; 2^N codes but 2^N − 1 steps.
Quantisation error - bounded by ±½ LSB for rounding; rms = Q/√12, irreducible.
Ideal SNR - 6.02N + 1.76 dB for a full-scale sine; about 6 dB per bit.
ENOB - (SINAD − 1.76)/6.02; the honest resolution of a real converter.
Nyquist criterion - f_s > 2f_m; anti-aliasing filter is mandatory, not optional.
Aliasing - irreversible folding of out-of-band energy into the baseband.
Sample-and-hold - holds the input steady during conversion; aperture error = 2πf·A·t_a.
R-2R ladder - two resistor values only; the practical, scalable DAC topology.
Binary-weighted DAC - simple but needs a 2^{N-1}:1 resistor spread; poor beyond a few bits.
Flash ADC - 2^N − 1 comparators, one clock, fastest, limited to ~6-8 bits.
SAR ADC - binary search, exactly N clocks, best speed-power-accuracy compromise; inside most MCUs.
Dual-slope ADC - ratio-metric, drift-cancelling, rejects 50 Hz when T₁ = k × 20 ms; used in multimeters.
Sigma-delta ADC - oversampling plus noise shaping; 16-24 bits at low bandwidth.
Oversampling gain - 3 dB (½ bit) per doubling without noise shaping; ≈ (6L+3) dB with an L-th order loop.
Pipeline ADC - high throughput with latency; the choice for 10-200 MSPS communications.
DNL and INL - step-to-step and overall linearity; DNL ≤ −1 LSB means a missing code.
Monotonicity - DAC output never falls as code rises; required in feedback loops.
Glitch impulse - worst at the major carry (0111→1000) because many switches change together.

Formulas and examples

Step size (1 LSB) Q = V_FS / 2^N [V]; V_FS = full-scale reference voltage, N = number of bits
DAC output V_o = V_ref × D / 2^N, where D = decimal equivalent of the input code
Full-scale DAC output V_o(max) = V_ref × (2^N − 1) / 2^N
Percentage resolution = 100 / (2^N − 1) [%]
ADC output code D = round( V_in × 2^N / V_FS ) (truncating converters use floor)
Quantisation noise rms = Q / √12 [V]; noise power = Q²/12
SNR_max = 6.02 N + 1.76 dB (full-scale sinusoid, ideal uniform quantiser)
ENOB = (SINAD − 1.76) / 6.02 [bits]
Nyquist: f_s > 2 f_m ; alias frequency f_alias = | f_in − k f_s |, k integer
Aperture (slew) error ΔV = A · 2π f · t_a [V]; t_a = aperture time in s
Oversampling SNR gain = 10 log₁₀ K dB (K = f_s / 2f_m, oversampling ratio)
SAR conversion time = N × T_clk ; Counter ADC worst case = (2^N − 1) × T_clk
Dual slope: V_in / V_ref = T₂ / T₁ , so count N₂ = N₁ × V_in / V_ref
S/H droop rate dV/dt = I_leak / C_H [V/s]

Example 1 — Resolution, code and output of a DAC. A 10-bit DAC has V_ref = 5.00 V.

Number of codes = 2¹⁰ = 1024; step size Q = 5.00/1024 = 4.883 mV.
Percentage resolution = 100/1023 = 0.0978 %.
Full-scale output = 5.00 × 1023/1024 = 4.9951 V (one LSB below 5 V).
Output for input code 1000000000₂ = 512: V_o = 5.00 × 512/1024 = 2.500 V.
Output for code 0000000001₂ = 1: V_o = 4.883 mV.

Example 2 — ADC code, quantisation error and SNR. A 12-bit unipolar ADC with V_FS = 3.30 V measures V_in = 1.000 V.

Q = 3.30/4096 = 805.66 µV.
Ideal code = 1.000/0.00080566 = 1241.2 → rounded code 1241 (decimal), i.e. 010011011001₂.
Voltage represented by code 1241 = 1241 × 805.66 µV = 0.99983 V → quantisation error = 1.000 − 0.99983 = 0.17 mV, well inside ±Q/2 = ±403 µV.
Quantisation noise rms = Q/√12 = 805.66 µV/3.464 = 232.6 µV.
Ideal SNR = 6.02 × 12 + 1.76 = 74.0 dB. If the measured SINAD is 68 dB, ENOB = (68 − 1.76)/6.02 = 11.0 bits — one bit lost to real-world noise.

Example 3 — Aliasing. A 2 kHz sine is sampled at 3 kHz with no anti-aliasing filter.

f_s/2 = 1.5 kHz, and 2 kHz > 1.5 kHz, so the signal is undersampled.
Alias = |2000 − 3000| = 1000 Hz. The recorded data shows a perfectly convincing 1 kHz tone that was never present.
To sample it properly, f_s must exceed 4 kHz (in practice 5-10 kHz with a real filter).

Example 4 — Aperture error fixes the S/H requirement. A 10 kHz, 2 V peak sine is digitised by a 12-bit ADC with V_FS = 4 V (so 1 LSB = 977 µV, ±½ LSB = 488 µV).

Maximum slew = A·2πf = 2 × 2π × 10,000 = 1.2566 × 10⁵ V/s.
Required aperture t_a ≤ 488 µV / 1.2566 × 10⁵ = 3.9 ns.
An unbuffered ADC with a 1 µs conversion window would be in error by 0.126 V (≈ 129 LSB) — hence the sample-and-hold.

Example 5 — Conversion time and architecture choice. Compare three 12-bit converters on a 20 MHz clock (T_clk = 50 ns).

SAR: 12 × 50 ns = 600 ns → about 1.6 MSPS (plus acquisition time).
Counter-type: worst case 4095 × 50 ns = 204.75 µs → under 5 kSPS.
Flash: one clock = 50 ns, but needs 4095 comparators — impractical at 12 bits.
A dual-slope part with T₁ = 100 ms (5 × 20 ms) rejects 50 Hz mains and gives about 5 readings/s — right for a multimeter, useless for an audio input.

Example 6 — Oversampling to save bits. An 8-bit ADC (ideal SNR 49.9 dB) is oversampled 64× and digitally filtered to the signal band.

SNR gain = 10 log₁₀ 64 = 18.06 dB → SNR ≈ 68.0 dB, i.e. ENOB ≈ (68.0 − 1.76)/6.02 = 11.0 bits.
Confirms the 3 dB (½ bit) per doubling rule: 6 doublings = 3 extra bits.

Architecture	Comparators / clocks	Typical bits	Typical speed	Where used
Flash	2^N − 1 comparators, 1 clock	4-8	100 MSPS - several GSPS	Oscilloscopes, radar, pipeline sub-ADCs
Pipeline	few per stage, 1 sample/clock + latency	8-16	10-500 MSPS	SDR, base stations, imaging
SAR	1 comparator, N clocks	8-18	kSPS - few MSPS	MCU ADCs, data acquisition, sensors
Sigma-delta	1-bit, oversampled	16-24	Hz - few hundred kSPS	Audio, weighing, energy meters
Dual-slope	integrator, up to 2 × 2^N clocks	3½-4½ digits	1-100 SPS	DMMs, panel meters
Counter/ramp	1 comparator, up to 2^N clocks	8-12	very low	Teaching, simple monitors

Error	Effect on transfer curve	Correctable in software?
Offset	Curve shifted up/down	Yes, subtract a constant
Gain	Wrong slope	Yes, scale by a factor
INL	Curve bends away from straight line	Only by a lookup table
DNL	Unequal steps, missing codes	No
Quantisation	Inherent staircase	No

Where it is used

Embedded and IoT products: every STM32/ESP32/PIC-based board uses its internal SAR ADC for temperature, current, battery and potentiometer sensing, and a PWM or string DAC for analog outputs — the daily work of embedded engineers at Bosch, Tata Elxsi, L&T Technology Services, HCL, Cyient.
Test and measurement: dual-slope and sigma-delta converters in digital multimeters and panel meters (Fluke, Rishabh, Meco, HTC); flash and pipeline ADCs in digital storage oscilloscopes.
Power and energy: Indian smart energy meters (Secure Meters, Genus, HPL, L&T) sample voltage and current with sigma-delta or SAR ADCs for energy, THD and tamper computation; inverters and motor drives sample phase currents synchronously with PWM.
Communications and defence: high-speed pipeline and flash ADCs/DACs in 4G/5G radios, software-defined radio, radar and satellite payloads — BEL, DRDO labs (LRDE, SAC), ISRO, Qualcomm, Nokia, Ericsson, Samsung R&D.
Audio, imaging and automotive: sigma-delta codecs in phones and audio equipment; CMOS image sensors with column-parallel SAR ADCs; automotive ECUs digitising lambda, knock and position sensors to BS-VI requirements.
VLSI and analog design roles: mixed-signal design, layout and validation of data converters is a standard interview area at Texas Instruments India, Analog Devices Bengaluru, Infineon, NXP, Renesas, Microchip, Silicon Labs and Indian design services firms.

Interview questions

Q: What is the resolution of a 12-bit ADC with a 5 V reference? A: 1 LSB = 5/4096 ≈ 1.22 mV; the converter has 4096 codes covering 0 to about 4.9988 V.
Q: Why is the ideal SNR 6.02N + 1.76 dB? A: It is the ratio of the rms of a full-scale sine (V_FS/2√2) to the quantisation noise rms (Q/√12), expressed in dB; the 1.76 dB comes from the sine-wave and uniform-noise factors.
Q: Why is an R-2R ladder preferred over a binary-weighted DAC? A: It needs only two resistor values regardless of word length, so ratio matching, trimming and IC integration are practical; a weighted DAC needs a 2^{N-1}:1 resistor spread.
Q: What happens if you sample a 6 kHz tone at 8 kHz? A: It aliases to |6000 − 8000| = 2 kHz and is indistinguishable from a real 2 kHz tone; only an anti-aliasing filter before sampling prevents it.
Q: Why does a dual-slope ADC reject mains hum? A: Its first integration averages the input over a fixed time; choosing that time as an integer multiple of 20 ms makes the average of a 50 Hz interference (and its harmonics) exactly zero.
Q: Which ADC is in a typical microcontroller and why? A: A SAR — it needs just one comparator and a DAC, takes a deterministic N clocks, gives 10-12 bits at hundreds of kSPS and consumes very little power and die area.
Q: Difference between latency and throughput in an ADC? A: Throughput is samples per second; latency is the delay from sampling an input to its code appearing. A pipeline ADC has one sample per clock but several clocks of latency — a problem in fast control loops.
Q: Why is a sample-and-hold needed before a SAR ADC? A: The binary search assumes a constant input; if the signal moves during the N clocks the comparisons are inconsistent. The S/H also bounds aperture error to a few nanoseconds.
Q: What does DNL = −1 LSB mean? A: The step has zero width — a missing code in an ADC, and in a DAC it signals the onset of non-monotonicity.
Q: How does a sigma-delta ADC achieve 24 bits with a 1-bit quantiser? A: Heavy oversampling plus a feedback loop that shapes quantisation noise out of the signal band, followed by digital decimation filtering; resolution is traded against bandwidth.
Q: Where does the worst DAC glitch occur? A: At the major-carry transition (for example 0111→1000), because many switches change state simultaneously and their timing mismatch momentarily produces a wrong output.
Q: Your 12-bit reading is noisy in the last three bits. What do you check first? A: The reference and supply — their noise, drift and decoupling — then grounding and the source impedance driving the sampling capacitor; the ADC core is rarely the cause.
Q: Can oversampling replace a higher-resolution ADC? A: Partly: without noise shaping you gain only ½ bit per doubling and only if the noise is white and uncorrelated with the signal; it cannot fix INL, offset or reference error.

Common mistakes

Using 2^N instead of 2^N − 1 for percentage resolution, or expecting full-scale output to equal V_ref exactly.
Writing SNR = 6N dB and dropping the 1.76 dB term, or applying the formula to a signal that is not full-scale.
Confusing the Nyquist rate (2f_m) with the Nyquist frequency (f_s/2).
Assuming an anti-aliasing filter after sampling can undo aliasing — it cannot; the damage is done at the sampler.
Quoting SAR conversion time as 2^N clocks (that is the counter-type ADC); SAR takes exactly N.
Treating ENOB as equal to N, and ignoring that reference noise and drift, not the bit count, often limit real accuracy.
Mixing truncation and rounding quantisers: truncation gives error 0 to −Q (a DC offset of ½ LSB), rounding gives ±Q/2.
Forgetting the source impedance and acquisition time, so the sampling capacitor never fully charges and every reading reads low.