Operational amplifiers

Electronics and Communication Engineering (B.E./B.Tech) · Circuits and devices · free study notes for exams, placements and interviews

In short

An operational amplifier is a high-gain, direct-coupled differential voltage amplifier built as an IC, intended to be used with external feedback so that the circuit's behaviour is set by resistor and capacitor ratios rather than by the device itself. Its open-loop gain is so large (10⁵ to 10⁶) that negative feedback makes the closed-loop gain almost perfectly predictable, which is why the same chip can be wired as an amplifier, adder, subtractor, integrator or buffer. Op-amps appear in every signal-conditioning chain in India - sensor front-ends, weighing machines, ECG amplifiers, inverters, instrumentation and automotive ECUs. The topic carries steady marks in university exams and GATE EC/EE/IN, and is standard interview ground at Texas Instruments India, Analog Devices, Infineon, Bosch, BEL, ISRO and ECIL.

Explained

What an op-amp is, inside and outside

Symbol: two inputs - inverting (−) and non-inverting (+) - one output, plus supply pins (usually ±15 V dual, or a single 5 V/3.3 V rail for modern parts).
Output depends only on the difference: Vo = A_OL (V⁺ − V⁻), where A_OL is the open-loop differential gain. Any voltage common to both inputs should ideally produce nothing.
Internal block chain: (1) differential input stage with a current-mirror active load - gives high gain, high CMRR, low offset; (2) intermediate gain stage (Darlington CE, level-shifted so the quiescent output is 0 V); (3) class-AB complementary push-pull output stage with short-circuit protection - gives low output impedance; (4) bias network of current mirrors and an on-chip frequency-compensation capacitor (30 pF in the 741, Miller-connected around the second stage).
IC 741 pinout (8-pin DIP): 1 offset null, 2 inverting input, 3 non-inverting input, 4 V−, 5 offset null, 6 output, 7 V+, 8 not connected.
Open loop, an op-amp is practically unusable as a linear amplifier: 200,000 × a 1 mV input would demand 200 V, so it simply saturates. Linear operation requires negative feedback.

Ideal op-amp and the two golden rules

Ideal assumptions: infinite open-loop gain, infinite input resistance (zero input current), zero output resistance, infinite bandwidth and slew rate, infinite CMRR, zero input offset voltage and zero drift, output 0 V for equal inputs.

Two rules follow, and almost every exam problem is solved with them:

No current enters either input terminal (Rin = ∞).
Virtual short: with negative feedback and finite output, V⁺ ≈ V⁻, because V⁺ − V⁻ = Vo/A_OL → 0. If the non-inverting input is grounded, the inverting input sits at 0 V without being connected to ground - a virtual ground.

Parameter	Ideal	IC 741 (typical)	Good modern part
Open-loop gain A_OL	∞	2 × 10⁵ (106 dB)	10⁶ or more
Input resistance	∞	2 MΩ	10¹² Ω (FET/CMOS input)
Output resistance	0	75 Ω	a few ohms
Bandwidth (unity gain)	∞	1 MHz	1 MHz to GHz
Slew rate	∞	0.5 V/µs	10-1000 V/µs
Input offset voltage Vos	0	2 mV (6 mV max)	25 µV (OP07)
Input bias current I_B	0	80 nA	pA (FET input)
CMRR	∞	90 dB	100-130 dB
PSRR	∞	30 µV/V	1-10 µV/V

Practical (non-ideal) parameters - what they cost you

Input offset voltage Vos: the differential input needed to bring the output to 0 V; caused by mismatch in the input pair. Amplified by the noise gain (1 + Rf/R1) and appears as a DC error at the output. Nulled by a 10 kΩ pot across pins 1 and 5 with the wiper to V− (741), or by choosing a precision op-amp.
Input offset voltage drift: change of Vos with temperature (µV/°C) and with time - cannot be trimmed away, so it limits DC precision.
Input bias current I_B: the average DC current the two inputs need; input offset current I_os = |I_B1 − I_B2|. Bias current through the feedback network creates another DC error, cancelled by making the resistance seen from both inputs equal (R_comp = R1 ∥ Rf), after which only I_os matters.
CMRR = 20 log (A_d/A_cm) in dB - ability to reject interference common to both inputs (mains hum, ground shift). Critical in difference amplifiers.
PSRR: change in Vos per volt of supply change; decides how much supply ripple leaks to the output.
Slew rate SR = dVo/dt|max (V/µs), set by the compensation capacitor and the current available to charge it: SR = I/C. It is a large-signal limit, independent of the small-signal bandwidth.
Finite A_OL: closed-loop gain error ≈ 1/(1 + Aβ), where β is the feedback factor. The product Aβ = loop gain governs accuracy, input/output impedance improvement and distortion reduction.
Output limits: saturation about 1-2 V inside each rail for a classic 741 (±13 V on ±15 V), rail-to-rail in modern CMOS parts; output current limited (±25 mA for 741).
Input common-mode range: the input voltages must stay within a specified band or the stage stops working; exceeding it in some bipolar parts can cause phase inversion or latch-up.
Noise: input-referred voltage noise (nV/√Hz) and current noise, plus 1/f flicker noise - decides the smallest sensor signal you can amplify.

Basic closed-loop configurations

Inverting amplifier: Vo/Vi = −Rf/R1. Input impedance = R1 (a disadvantage); the virtual ground keeps the inverting node at 0 V, so there is no common-mode swing at the input - good for high gain and high-frequency work.
Non-inverting amplifier: Vo/Vi = 1 + Rf/R1; input impedance is very high (Ri × (1 + Aβ)); gain cannot be less than 1.
Voltage follower (unity-gain buffer): output tied to the inverting input, Vo = Vi, gain exactly 1, highest input and lowest output impedance - used as an impedance isolator between a high-impedance sensor and a load or an ADC.
Summing (inverting adder): Vo = −Rf (V1/R1 + V2/R2 + V3/R3); each input sees its own resistor to the virtual ground, so the channels do not interact - the classic audio mixer and DAC input network.
Difference (subtractor) amplifier: with R1 = R3 and R2 = R4, Vo = (R2/R1)(V2 − V1). Its real CMRR is limited by resistor mismatch, not by the op-amp: CMRR ≈ (1 + R2/R1)/(4δ) for fractional tolerance δ. Cascading three op-amps gives the instrumentation amplifier, with high input impedance on both inputs.
Integrator: Vo = −(1/RC)∫Vi dt. A large resistor Rf across C is always added to stop DC offset from ramping the output into saturation; the circuit integrates properly for f ≫ 1/(2πRfC).
Differentiator: Vo = −RC dVi/dt. Gain rises with frequency, so it amplifies noise and tends to oscillate; a small series resistor with C and a small capacitor across R are added to limit high-frequency gain.
V-to-I and I-to-V converters: a resistor in the feedback path converts a photodiode or 4-20 mA loop current into a voltage (transimpedance amplifier, Vo = −I × Rf).
Single-supply operation: the inputs are biased to a mid-rail reference (Vcc/2) through a divider and the signal is AC-coupled - standard practice with LM324/LM358 in 5 V systems.

Frequency response, bandwidth and stability

An internally compensated op-amp has a dominant pole (about 5 Hz in the 741), so A(f) = A_OL/(1 + jf/f1) and the gain falls at −20 dB/decade to unity gain at f_T.
Gain-bandwidth product is constant: A_CL × BW ≈ f_T. A 741 (f_T = 1 MHz) gives 1 MHz at unity gain, 10 kHz at a gain of 100. Trading gain for bandwidth is why multistage low-gain designs beat one high-gain stage.
Negative feedback widens bandwidth by (1 + Aβ), raises input impedance by the same factor in the non-inverting case, divides output impedance by it, and reduces distortion and gain sensitivity to the same degree - the price is loss of gain.
Stability: the circuit oscillates if the loop gain reaches 1 while the phase lag reaches 180°. Internal (Miller) compensation makes the part unity-gain stable; decompensated parts are faster but stable only above a minimum gain.
A capacitive load adds a pole at the output and can cause ringing or oscillation; remedies are a small series isolation resistor (10-100 Ω), or an out-of-loop snubber.
Full-power bandwidth from slew rate: f_max = SR/(2πVp). This, not the small-signal bandwidth, is usually the limit for large outputs; exceeding it turns a sine wave into a triangle.
Good practice: decoupling capacitors (0.1 µF ceramic) close to the supply pins, short feedback loops, low-leakage layout around high-impedance nodes.

Classification of op-amps and selection

General purpose: 741, LM358/LM324 (single supply, dual/quad) - cheap, adequate for DC and audio.
FET/CMOS input: TL081/LF351 (JFET), CA3140, MCP600x - picoamp bias current for photodiodes, pH meters, integrators.
Precision/low drift: OP07, OP27, chopper-stabilised zero-drift parts - Vos in microvolts for bridge and thermocouple front-ends.
Low noise, high speed, high voltage, low power, rail-to-rail I/O, current-feedback families exist for specific needs; a current-feedback amplifier has a gain-independent bandwidth but cannot be used with a capacitor in feedback.
Comparators (LM311, LM393) are open-loop devices with digital outputs; an op-amp can be used as a slow comparator but has no hysteresis, slow recovery from saturation and no logic-compatible output.
Selection order in practice: supply rails and input/output range → DC accuracy (Vos, drift, I_B) → bandwidth and slew rate → noise → power and package.
Quality/qualification grades referenced in Indian industry: commercial/industrial/military temperature ranges, MIL-STD-883 screening for defence and space builds (BEL, ISRO), AEC-Q100 for automotive parts; the finished equipment is then certified under the relevant IS/IEC safety and EMC standards (for example IS 13252 / IEC 62368-1 for IT and audio-video equipment, and CE/BIS marking as applicable). Grade designations vary by manufacturer - check the specific datasheet.

Key points

Op-amp - very high gain differential DC amplifier designed to be used with negative feedback.
Ideal model - A = ∞, Rin = ∞, Rout = 0, BW = ∞, CMRR = ∞, Vos = 0.
Virtual short - V⁺ ≈ V⁻ whenever negative feedback holds the output out of saturation; becomes a virtual ground if V⁺ is grounded.
Inverting gain - −Rf/R1, input impedance R1; non-inverting gain - 1 + Rf/R1, input impedance very high.
Voltage follower - unity gain impedance buffer; best choice ahead of an ADC or a low-impedance load.
Loop gain Aβ - decides accuracy; gain error ≈ 1/(1 + Aβ), impedances improve by (1 + Aβ).
Gain-bandwidth product - constant for an internally compensated op-amp; BW = f_T/A_CL.
Slew rate - large-signal limit, V/µs; full-power bandwidth = SR/(2πVp).
Offset voltage error - Vos × (1 + Rf/R1) appears at the output regardless of signal.
Bias-current error - cancelled by R_comp = R1 ∥ Rf, leaving only I_os × Rf.
CMRR - 20 log(A_d/A_cm); in a difference amplifier, resistor tolerance usually sets the real CMRR.
PSRR - supply-ripple rejection, quoted in µV/V or dB.
Integrator - −(1/RC)∫Vi dt, needs a DC-limiting resistor across C; differentiator - −RC dVi/dt, needs HF gain limiting.
Summing amplifier - channels are independent because each input drives a virtual ground.
741 benchmarks worth remembering - A = 2 × 10⁵, f_T = 1 MHz, SR = 0.5 V/µs, Vos = 2 mV, I_B = 80 nA, CMRR = 90 dB, Rout = 75 Ω.
Saturation - output clamps 1-2 V inside the rails (rail-to-rail parts get within millivolts).
Single supply - bias inputs at mid-rail and AC-couple; otherwise negative signal excursions clip.
Op-amp vs comparator - feedback and linear operation vs open loop and digital output.

Formulas and examples

Open loop: Vo = A_OL (V⁺ − V⁻); A_OL(dB) = 20 log₁₀ A_OL
Inverting: A_CL = −Rf/R1; Zin = R1
Non-inverting: A_CL = 1 + Rf/R1; feedback factor β = R1/(R1 + Rf)
With finite gain: A_CL = A/(1 + Aβ); fractional gain error ≈ 1/(1 + Aβ)
Zin(non-inv) = Ri(1 + Aβ); Zout = Ro/(1 + Aβ)
Summing: Vo = −Rf(V1/R1 + V2/R2 + V3/R3)
Difference: Vo = (R2/R1)(V2 − V1) for R1 = R3, R2 = R4
Integrator: Vo(t) = −(1/RC)∫Vi dt + Vo(0); Differentiator: Vo = −RC dVi/dt
Bandwidth: A_CL × BW = f_T (unity-gain frequency, Hz)
Slew rate SR = dVo/dt|max (V/µs); full-power bandwidth f_max = SR/(2πVp)
CMRR(dB) = 20 log₁₀(A_d/A_cm); output CM error = A_cm × V_cm
DC errors: Vo(offset) = Vos(1 + Rf/R1) + I_os × Rf (with R_comp = R1 ∥ Rf fitted)
Symbols: Rf feedback resistor (Ω), R1 input resistor (Ω), C in farads, Vp peak output (V), f in Hz, I in amperes.

Example 1 - inverting amplifier, then used as an adder. Rf = 47 kΩ, R1 = 2.2 kΩ, Vi = 100 mV DC, supplies ±15 V.

A_CL = −47/2.2 = −21.36; Vo = −21.36 × 0.1 = −2.136 V (well inside the ±13 V swing).
Input impedance = R1 = 2.2 kΩ only, so the source must be stiff.
Now reuse the same op-amp as an adder with Rf = 100 kΩ, V1 = +0.5 V through 10 kΩ, V2 = −0.2 V through 20 kΩ: Vo = −100k × (0.5/10k − 0.2/20k) = −100k × (50 µA − 10 µA) = −100k × 40 µA = −4.0 V.

Example 2 - bandwidth and slew-rate limits of a 741. Non-inverting amplifier, Rf = 39 kΩ, R1 = 1 kΩ, Vi = 0.2 V peak sine.

A_CL = 1 + 39 = 40; Vo = 8 V peak.
β = 1/40, loop gain Aβ = 2 × 10⁵/40 = 5,000 → gain error ≈ 1/5,001 = 0.02%, so 40 is accurate enough.
Small-signal bandwidth = f_T/A_CL = 1 MHz/40 = 25 kHz.
Slew rate needed at 25 kHz for 8 V peak: 2πfVp = 2π × 25,000 × 8 = 1.26 × 10⁶ V/s = 1.26 V/µs - more than the 741's 0.5 V/µs.
So the real limit is the full-power bandwidth: f_max = 0.5 × 10⁶/(2π × 8) = 9.95 kHz. Above this the 8 V sine becomes triangular even though the small-signal bandwidth is 25 kHz.
Also Zout = 75/5,001 = 15 mΩ (in-band) - the follower-like stiffness that feedback buys.

Example 3 - DC error budget. 741 inverting amplifier, R1 = 1 kΩ, Rf = 100 kΩ, Vos = 2 mV, I_B = 80 nA, I_os = 20 nA.

Noise gain = 1 + 100k/1k = 101 → output error from offset voltage = 2 mV × 101 = 202 mV.
With no compensating resistor, bias-current error = I_B × Rf = 80 nA × 100 kΩ = 8 mV.
Fit R_comp = R1 ∥ Rf = (1k × 100k)/101k = 990 Ω in the non-inverting lead; the error drops to I_os × Rf = 20 nA × 100 kΩ = 2 mV.
Worst-case DC output offset ≈ 202 + 2 = 204 mV - unacceptable for a DC measurement, which is exactly why an OP07 (Vos = 25 µV → 2.5 mV output error) is used in bridge amplifiers.

Example 4 - common-mode error in a difference amplifier. A_d = 100, CMRR = 90 dB, common-mode input 2 V (sensor sitting on a 2 V pedestal).

A_cm = A_d/10^90/20 = 100/31,623 = 3.16 × 10⁻³.
Output error = 3.16 × 10⁻³ × 2 V = 6.32 mV, i.e. 63.2 µV referred to the input - equivalent to a 0.63% error if the real signal is 10 mV full scale… acceptable here.
But with 1% resistors and unity gain, resistor-mismatch CMRR ≈ (1 + 1)/(4 × 0.01) = 50 → 34 dB only, giving a 40 mV output error for the same 2 V - the resistors, not the op-amp, dominate. Use 0.1% matched networks.

Example 5 - integrator as a square-to-triangle converter. R = 10 kΩ, C = 0.01 µF, input ±2 V square wave at 5 kHz, Rf = 100 kΩ across C.

RC = 10 × 10³ × 0.01 × 10⁻⁶ = 100 µs; ramp slope = Vi/RC = 2/100 µs = 0.02 V/µs.
Half period = 100 µs → output swing = 0.02 × 100 = 2 V, so a 2 V peak-to-peak triangular wave, inverted and phase-shifted 90°.
Lower corner from Rf: f = 1/(2πRfC) = 1/(2π × 100k × 0.01µ) = 159 Hz; true integration needs f ≫ 159 Hz, and 5 kHz is 31× higher - satisfied.

Configuration	Gain	Zin	Phase	Typical use
Inverting	−Rf/R1	R1	180°	Gain stage, adder, virtual-ground node
Non-inverting	1 + Rf/R1	Very high	0°	Sensor amplification
Voltage follower	1	Highest	0°	Buffer, ADC driver
Difference	(R2/R1)(V2−V1)	Moderate	-	Bridge, current-shunt sensing
Integrator	−1/jωRC	R	−	Ramp generation, control loops
Differentiator	−jωRC	1/jωC	−	Rate/edge detection

Where it is used

Sensor signal conditioning: load-cell weighbridges and retail weighing scales, RTD/thermocouple transmitters, pressure transmitters for 4-20 mA loops - difference and instrumentation amplifiers with precision op-amps.
Medical electronics: ECG, EEG and pulse-oximetry front-ends, where CMRR above 100 dB rejects 50 Hz mains pickup from the patient's body - a core design task at companies making Indian-market patient monitors.
Power electronics and automotive: current-shunt and Hall-sensor amplifiers, gate-drive level shifting, error amplifiers in solar inverters and UPS feedback loops (Delta, Schneider, Luminous, Bosch, Tata Elxsi, KPIT).
Industrial instrumentation and process control: isolation buffers, V-to-I and I-to-V converters, PLC analogue input cards; also PID controller blocks built as summer-integrator-differentiator chains.
Defence, space and test gear: BEL, DRDO labs, ISRO/ECIL use screened op-amps in radar receivers, telemetry conditioning and avionics; analogue design and validation roles at Texas Instruments India, Analog Devices and Infineon in Bengaluru work on the devices themselves.
Job roles: analogue design engineer, hardware/board design engineer, test and validation engineer, applications engineer, instrumentation engineer - all of whom are asked op-amp questions in the technical round.

Interview questions

Q: Why can an op-amp not be used open loop as a linear amplifier? A: Its gain is so high (about 2 × 10⁵) that even a millivolt of input drives the output into saturation; negative feedback is needed to define a usable, stable gain.
Q: What is a virtual ground and when does it exist? A: When the non-inverting input is grounded and negative feedback holds the output in the linear region, the inverting input is forced to nearly 0 V without a physical connection to ground.
Q: An inverting amplifier has Rf = 100 kΩ and R1 = 10 kΩ. What are the gain and input impedance? A: Gain = −10, and the input impedance is just R1 = 10 kΩ, which is why the non-inverting configuration is chosen for high-impedance sources.
Q: What is the difference between bandwidth and slew rate? A: Bandwidth is a small-signal limit set by the dominant pole and the closed-loop gain; slew rate is a large-signal limit on how fast the output voltage itself can change, set by the compensation capacitor's charging current.
Q: A 741 has f_T = 1 MHz. What bandwidth do you get at a gain of 100? A: About 10 kHz, since gain × bandwidth is constant for an internally compensated op-amp.
Q: Why do we add a resistor in the non-inverting lead of an inverting amplifier? A: To make the DC resistance seen from both inputs equal (R1 ∥ Rf) so the bias currents produce equal and opposing drops, leaving only the much smaller offset-current error.
Q: Why is a resistor placed across the capacitor in a practical integrator? A: The capacitor is an open circuit at DC, so offset voltage and bias current would integrate until the output saturates; the resistor sets a finite DC gain and a lower frequency limit.
Q: What limits the CMRR of a four-resistor difference amplifier? A: Resistor mismatch, not the op-amp - 1% resistors can cut the CMRR to around 34 dB at unity gain, which is why matched networks or an instrumentation amplifier are used.
Q: Can a voltage follower have a gain greater than one? A: No. Its feedback factor is unity, so the gain is 1 (slightly less than 1 because of finite open-loop gain); for gain above 1 you need the non-inverting configuration.
Q: Why is an op-amp a poor comparator? A: It is internally compensated for slow linear operation, recovers slowly from saturation, has no hysteresis and its output does not swing to logic levels; a dedicated comparator is faster and logic-compatible.
Q: What happens if you drive a long cable or a large capacitor directly from an op-amp output? A: The load capacitance adds a pole inside the feedback loop, reducing phase margin and causing ringing or oscillation; a small series isolation resistor restores stability.
Q: How do you run a 741-type circuit on a single 5 V supply? A: Bias both inputs to a mid-rail reference (2.5 V) through a divider and AC-couple the signal - though a true single-supply part such as the LM324, or better a rail-to-rail CMOS op-amp, is the right choice, since the 741 needs a wider supply and cannot swing near the rails.

Common mistakes

Applying the virtual-short rule when the op-amp is saturated or when feedback is positive - it holds only for negative feedback with the output in the linear region.
Assuming the inverting amplifier has infinite input impedance; it is R1, because the signal source drives a virtual ground.
Computing a gain-bandwidth answer and forgetting to check the slew-rate (full-power bandwidth) limit, which usually bites first for large outputs.
Forgetting the noise-gain multiplication of Vos - a 2 mV offset becomes 200 mV at a gain of 100, which can swamp a small DC signal.
Taking the ideal gain formula as exact in precision work instead of allowing the 1/(1 + Aβ) error, and ignoring resistor tolerance in difference amplifiers.
Building a plain differentiator and then wondering why it oscillates or amplifies noise - its gain rises with frequency and must be rolled off.
Omitting supply decoupling capacitors, long feedback traces, or leaving unused sections of a quad op-amp with floating inputs - all common lab causes of oscillation and drift.