CMOS digital IC design

In short

CMOS digital IC design is the craft of building logic gates, flip-flops and memory cells from complementary nMOS and pMOS transistors, then sizing and arranging them to meet targets for delay, power, area and noise. It matters because essentially every digital chip shipped today — processors, SoCs, memories, microcontrollers — is CMOS, and because the same transistor-level reasoning explains why a design is fast, leaky or robust. It is heavily examined in GATE EC/EE (switching threshold, delay, power, logic realisation), in university VLSI Design papers under AICTE/CBCS curricula, and in placement technical rounds. Indian employers testing it include Intel, Qualcomm, Samsung SRI-B, Texas Instruments, NXP, AMD, Nvidia, Micron, Cadence, Synopsys, Tessolve, Sankalp, Einfochips and the SCL Mohali / ISRO / DRDO ecosystem, as well as design-linked incentive-era fabs and ATMP units.

Explained

MOSFET as a switch and the basic device equations

• An enhancement nMOS conducts when V_GS > V_tn and passes a strong 0; a pMOS conducts when V_SG > |V_tp| and passes a strong 1. CMOS exploits this complementarity: only one network conducts in steady state, so static current is ideally zero.
• Regions: cut-off (V_GS < V_t, I_D ≈ 0 except subthreshold), linear/triode (V_DS < V_GS − V_t, resistive), saturation (V_DS ≥ V_GS − V_t, current nearly constant). V_ov = V_GS − V_t is the overdrive.
• Body effect: a source raised above the body increases V_t, V_t = V_t0 + γ(√(|2φ_F| + V_SB) − √|2φ_F|). This is why stacked transistors and pass-transistor outputs are slower and degraded.
• Short-channel effects at deep submicron: velocity saturation (current becomes roughly linear in V_ov, not square-law), channel-length modulation, DIBL (drain-induced barrier lowering reduces V_t), mobility degradation by the vertical field, and hot-carrier / oxide reliability limits. Hence modern short-channel current is often modelled as I_D ≈ W·v_sat·C_ox·(V_ov − V_Dsat).
• Process transconductance: k_n' = μ_n C_ox, with C_ox = ε_ox/t_ox. Electron mobility is about 2-3× hole mobility, so for equal strength W_p ≈ 2-3 W_n (commonly taken as 2 or 2.5 in exams; the exact ratio is process-specific).

The CMOS inverter: VTC, switching threshold, noise margins

• Structure: pMOS from V_DD to output (gate tied to input), nMOS from output to ground. Input low → pMOS on, output = V_DD; input high → nMOS on, output = 0.
• Five regions of the VTC: (1) nMOS off, pMOS linear — output = V_DD; (2) nMOS saturated, pMOS linear; (3) both saturated — the steep transition at V_M; (4) nMOS linear, pMOS saturated; (5) pMOS off — output = 0.
• Switching threshold V_M is where V_out = V_in. Equating saturation currents gives V_M = [V_tn + r(V_DD − |V_tp|)] / (1 + r) with r = √(k_p/k_n) = √((W/L)_p μ_p / ((W/L)_n μ_n)). Symmetric VTC (V_M = V_DD/2) needs k_p = k_n, i.e. (W/L)_p = (μ_n/μ_p)(W/L)_n.
• Noise margins: NM_H = V_OH − V_IH, NM_L = V_IL − V_OL, where V_IL and V_IH are the unity-gain points of the VTC. Static CMOS gives V_OH = V_DD, V_OL = 0 — full logic swing, so noise margins are the best of any logic family.
• Ratioless: the logic levels do not depend on the W/L ratio (unlike nMOS or pseudo-nMOS logic); the ratio only shifts V_M and the rise/fall symmetry.
• Regenerative property: gain |dV_out/dV_in| ≫ 1 in the transition region restores degraded levels, which is why long logic chains do not accumulate noise.

Static CMOS combinational logic and layout

• Construction rule: realise the complement of the function in the pull-down network (PDN) with nMOS — series for AND terms, parallel for OR terms — and the dual network in the pull-up (pMOS), where series becomes parallel. Static CMOS is naturally inverting: a CMOS gate alone can produce NAND/NOR/AOI/OAI, never non-inverted AND/OR without an extra inverter.
• Transistor count for a complex gate = 2 × (number of literals). Example: Y = ((A+B)·C)' uses A‖B in series with C in the PDN, A series B in parallel with C in the PUN — 6 transistors, versus a gate-level build needing many more.
• Sizing for equal drive: in a k-input NAND, k nMOS in series → each nMOS width ×k; pMOS are parallel so each stays at the unit pMOS width (2 for a β ratio of 2). In a k-input NOR, pMOS stack → each pMOS ×2k. Therefore NAND is preferred over NOR in CMOS — the slow pMOS should never be stacked.
• Fan-in and fan-out: delay grows roughly quadratically with fan-in (more series resistance and more internal capacitance), so fan-in is limited to about 4 and wide functions are built as trees of 2-3 input gates with buffers.
• Layout: stick diagrams fix the relative placement of diffusion, poly, metal and contacts; a single unbroken diffusion strip for the whole gate needs an Euler path common to the PUN and PDN graphs. λ-based design rules (Mead-Conway style) are taught for scalability; real foundries give micron rules and DRC decks.
• Latch-up: the parasitic n-p-n / p-n-p pair in the well-substrate structure can form a self-sustaining SCR shorting V_DD to ground. Prevented by plenty of well and substrate taps/guard rings, low-resistance substrate (epitaxial layer), and spacing rules.

Other logic styles

• Transmission gate (TG): nMOS + pMOS in parallel with complementary gate signals; passes both 0 and 1 without threshold loss, resistance roughly constant over the swing. A 2:1 mux is 2 TGs (4 transistors); an XOR is 2 TGs + inverters; TG-based D latches are standard-cell practice.
• Pass-transistor logic (PTL): nMOS only — fewer transistors, but output rises only to V_DD − V_tn (level degradation), causing static leakage in the following inverter; needs level-restoring (swing-restoring) feedback pMOS.
• Pseudo-nMOS: PDN with a single always-on pMOS load. Half the transistors of static CMOS, good for wide NORs, but V_OL ≠ 0, ratioed logic, and continuous static power when the output is low.
• Dynamic (clocked) logic: precharge phase (clock low: pMOS precharges output to V_DD) then evaluate phase (clock high: footer nMOS on, PDN conditionally discharges). Fewer transistors, no ratio problem, lower input capacitance, but suffers charge leakage, charge sharing, clock feedthrough and cannot be cascaded directly (a falling input during evaluate causes false discharge).
• Domino logic: dynamic gate followed by a static inverter, so inter-stage signals only rise during evaluate — cascadable and fast, but only non-inverting functions; NP-CMOS / NORA and zipper alternate n- and p-blocks to allow inversions. A small keeper pMOS holds the node against leakage.
• DCVSL / CPL (differential cascode voltage switch logic, complementary pass-transistor logic) give both polarities with cross-coupled loads; used in fast arithmetic blocks.

Delay, sizing and interconnect

• Propagation delay t_p is measured at 50% points; rise/fall times at 10-90%. A first-order model treats a gate as a resistance R driving load capacitance C_L: t_pHL = 0.69 R_n C_L, t_pLH ≈ 0.69 R_p C_L for a step input, giving t_p = (t_pHL + t_pLH)/2.
• Load capacitance = self (drain junction + gate-drain overlap, including Miller multiplication ×2 for C_gd) + fan-out gate capacitance + wire capacitance.
• Logical effort method: d = g·h + p, where g is logical effort (1 for an inverter, 4/3 for a 2-NAND, 5/3 for a 2-NOR with β = 2), h = C_out/C_in is the electrical effort, and p is parasitic delay. For an N-stage path, minimum delay occurs when each stage carries equal stage effort f = (GBH)^1/N, where G = Πg, B = branching, H = overall electrical effort. Optimum f ≈ 3.6-4 (often taken as e ≈ 2.72 with zero parasitics).
• Inverter chain / buffer sizing: to drive a large load, N = ln(F)/ln(f) stages with each stage scaled by f; this is the standard GATE question on buffer tapering.
• Interconnect: RC wire delay grows with the square of the length (50% delay of a distributed line ≈ 0.38 R_w C_w L², its Elmore delay R_w C_w L²/2, versus 0.69 RC for a lumped RC), so long nets are repeater-inserted; crosstalk and coupling capacitance set signal-integrity limits. Scaling improves transistors but not wires — hence copper interconnect and low-k dielectrics.

Power dissipation and low-power design

• Three components: dynamic switching (charging load caps), short-circuit (both devices momentarily on during the transition, typically 5-15% of dynamic), and static leakage (subthreshold, gate-oxide tunnelling, junction, GIDL).
• Dynamic power P_dyn = α C_L V_DD² f, where α is the activity factor. V_DD² dependence makes voltage scaling the single most effective lever, but delay rises as V_DD approaches V_t — hence multi-V_DD and DVFS (dynamic voltage and frequency scaling).
• Leakage rises exponentially as V_t falls: I_sub = I_0 e^{(V_GS − V_t)/(nV_T)}(1 − e^−V_DS/V_T). Counters: multi-V_t cells (HVT on non-critical paths), stack forcing, power gating with sleep transistors (MTCMOS), body/back biasing, and FinFET/GAA devices whose better gate control sharply cuts subthreshold slope degradation.
• Clock gating removes α on idle registers and is the first-line RTL/physical low-power technique; operand isolation, memory banking and retention flops follow. UPF/CPF describe power intent in industrial flows.
• Energy-delay product is the fair figure of merit; minimum-energy operation sits near-threshold, well below maximum frequency.

Sequential elements and memory

• Latch vs flip-flop: a latch is level-sensitive (transparent while the clock is active); a flip-flop is edge-triggered, usually two opposite-phase latches in a master-slave chain. TG-based or C²MOS implementations are standard.
• Timing constraints: t_setup and t_hold at the data input; for correct operation T_clk ≥ t_cq + t_logic,max + t_setup + t_skew, and hold is satisfied if t_cq + t_logic,min ≥ t_hold + t_skew. Setup violations are fixed by slowing the clock or speeding logic; hold violations cannot be fixed by slowing the clock — buffers must be added.
• Metastability occurs when data changes near the clock edge; resolution time is probabilistic, quantified by MTBF, and handled with two-flop synchronisers across clock domains.
• Clock distribution: H-tree and mesh networks minimise skew; the clock network is often the largest single power consumer.
• SRAM 6T cell: two cross-coupled inverters with two access nMOS. Read stability needs the cell ratio (driver/access strength) large enough to avoid flipping the cell (read static noise margin, butterfly curve); writeability needs the pull-up ratio small enough for the access device to overpower the pMOS. DRAM is 1T-1C, needs refresh and destructive sense amplification; ROM/Flash use floating-gate or charge-trap devices.

Scaling, standard cells and practice

• Constant-field (full) scaling by factor S: dimensions, t_ox, V_DD all /S → delay /S, power per gate /S², density ×S², power density constant. Constant-voltage scaling holds V_DD, giving higher power density — a reason Dennard scaling broke around the 90 nm era and clock frequencies plateaued.
• Devices have moved planar → FinFET (around 22-16 nm) → gate-all-around nanosheet at leading nodes; node names today are marketing labels, not physical gate lengths.
• Digital design is done with standard cell libraries (fixed height, characterised .lib timing/power, LEF abstracts) by synthesis and place-and-route, but hand transistor-level design survives in memories, I/O, clock cells and custom datapaths.
• Indian context: design rules and electrical limits come from foundry PDKs (TSMC, Samsung, GlobalFoundries, SCL Mohali's 180 nm line for strategic use). Interfaces follow JEDEC standards (JESD8 for LVCMOS logic levels, DDR standards); ESD/latch-up qualification follows JEDEC JESD22/JS-001 and AEC-Q100 for automotive. Programme-level support in India sits under the India Semiconductor Mission (MeitY) with the Semicon India programme and the Chips to Startup (C2S) scheme giving colleges EDA access — scheme terms and outlay change, so verify current notifications.

Key points

• CMOS complementarity - pull-up and pull-down networks are logical duals, so only one conducts in steady state; ideally zero static current.
• Ratioless logic - V_OH = V_DD and V_OL = 0 regardless of W/L; the ratio sets V_M and rise/fall symmetry only.
• Switching threshold - V_M = [V_tn + r(V_DD − |V_tp|)]/(1 + r), r = √(k_p/k_n); symmetric needs (W/L)_p ≈ 2-3 (W/L)_n.
• Noise margin - NM_H = V_OH − V_IH and NM_L = V_IL − V_OL; full-swing CMOS has the largest margins of all logic families.
• Dual network rule - series in PDN ↔ parallel in PUN; 2 transistors per literal; static CMOS gates are always inverting.
• NAND over NOR - stacking slow pMOS in a NOR forces ×2k pMOS widths; NAND stacks the faster nMOS.
• Fan-in limit - delay rises roughly as the square of fan-in; keep fan-in ≤ 4 and use gate trees.
• Transmission gate - nMOS‖pMOS passes full swing; nMOS-only pass logic loses V_tn and needs a level restorer.
• Dynamic logic - precharge then evaluate; fast and compact but suffers charge sharing, leakage and non-cascadability; domino fixes cascading at the cost of inverting functions.
• Delay model - t_p = 0.69 R_eq C_L; logical effort d = gh + p with equal stage effort f = (GBH)^1/N for minimum path delay.
• Buffer tapering - optimum stages N = ln F / ln f, f ≈ 3.6-4 in practice, e with zero parasitics.
• Dynamic power - P = αC V_DD² f; voltage scaling is quadratically effective, clock gating attacks α.
• Leakage - subthreshold current is exponential in −V_t; countered by multi-V_t, power gating, stacking and FinFET/GAA devices.
• Short-circuit power - occurs while both devices conduct; minimised by matching input and output slopes.
• Timing - T_clk ≥ t_cq + t_logic + t_setup + t_skew; hold violations need added delay, not a slower clock.
• SRAM 6T - cell ratio governs read stability, pull-up ratio governs writeability; sized by SNM butterfly analysis.
• Latch-up - parasitic SCR between well and substrate; prevented by guard rings, substrate/well taps and epi layers.
• Scaling - constant-field scaling keeps power density constant; its breakdown (leakage, V_DD floor) ended frequency scaling and forced multicore.

Formulas and examples

Example 1 - Switching threshold and resizing. Given V_DD = 1.8 V, V_tn = 0.45 V, |V_tp| = 0.45 V, k_n' = 270 µA/V², k_p' = 90 µA/V², (W/L)_n = (W/L)_p = 2.

• r = √(90 × 2 / (270 × 2)) = √(1/3) = 0.577.
• V_M = [0.45 + 0.577(1.8 − 0.45)]/(1 + 0.577) = (0.45 + 0.779)/1.577 = 1.229/1.577 = 0.78 V — below V_DD/2 = 0.9 V, so the inverter is nMOS-strong and switches early.
• For a symmetric VTC we need r = 1, i.e. k_p'(W/L)_p = k_n'(W/L)_n → (W/L)_p = 2 × 270/90 = 6, a 3:1 pMOS-to-nMOS ratio. Check: r = √(90×6/(270×2)) = √(540/540) = 1 → V_M = (0.45 + 1.35)/2 = 0.90 V. ✔

Example 2 - Delay and sizing of a NAND gate chain. Unit inverter: C_in = 3 fF, parasitic delay p = 1 (in units of τ), τ = 20 ps. A 2-input NAND (g = 4/3, p = 2) with C_in = 4 fF drives a load of 16 fF.

• h = 16/4 = 4 → d = g·h + p = (4/3)(4) + 2 = 5.33 + 2 = 7.33 τ = 147 ps.
• Now drive the same 16 fF through two stages: NAND (g = 4/3) + inverter (g = 1). G = 4/3, H = 16/4 = 4, B = 1 → F = 5.33, f = √5.33 = 2.31.
• Stage delays: 2 × 2.31 = 4.62, plus parasitics p = 2 + 1 = 3 → d = 7.62 τ = 152 ps. The extra inverter does not pay here because H is small; adding stages helps only when F is large (as a rule of thumb, when F > ~6-8 per extra stage).

Example 3 - Dynamic power and leakage budget. A block has 2 million gates, average switched capacitance 4 fF per gate, activity factor α = 0.1, V_DD = 1.0 V, f = 500 MHz.

• Total switched capacitance per cycle = 2 × 10⁶ × 4 fF × 0.1 = 0.8 nF effective.
• P_dyn = 0.8 × 10⁻⁹ × 1.0² × 500 × 10⁶ = 0.40 W.
• Scale V_DD to 0.8 V at the same frequency: P_dyn = 0.8 × 10⁻⁹ × 0.64 × 500 × 10⁶ = 0.256 W, a 36% saving (the V_DD² law) — provided timing still closes.
• Leakage: if each gate leaks 20 nA at V_DD = 1.0 V, P_leak = 2 × 10⁶ × 20 nA × 1.0 V = 40 mW, i.e. 10% of dynamic power at full activity, but 100% of the power when the block is idle — the case for power gating.

Example 4 - Clock period and hold check. A pipeline stage has t_cq = 90 ps, t_setup = 60 ps, t_hold = 40 ps, worst-case logic 540 ps, best-case logic 25 ps, clock skew 30 ps.

• Setup: T_clk ≥ 90 + 540 + 60 + 30 = 720 ps → f_max = 1/720 ps ≈ 1.39 GHz.
• Hold: required t_cq + t_logic,min ≥ t_hold + t_skew → 90 + 25 = 115 ps vs 40 + 30 = 70 ps → margin +45 ps, hold is met.
• If best-case logic were only 5 ps: 90 + 5 = 95 ps ≥ 70 ps still holds; a violation would need delay buffers on the short path, since lowering the frequency would not help.

Example 5 - Transistor sizing of a complex gate. Realise Y = (A·B + C)' with a unit nMOS width W and β = 2 (pMOS twice as wide for equal strength).

• PDN: A series B, that pair in parallel with C. PUN (dual): A parallel B, that pair in series with C.
• Sizing for inverter-equivalent drive: the A-B series nMOS path has 2 devices → each 2W; C alone in the PDN → W. In the PUN, C is in series with the A‖B pair → C needs 2 × 2W_p-unit = 4W, and A, B each 4W as well (each is in a 2-high pMOS stack of width-2 base).
• Transistor count = 6 for a function that would take roughly 14-16 transistors as an AND + OR + inverter cascade.

Where it is used

• SoC and processor design houses in India: Intel Bengaluru, Qualcomm (Bengaluru, Hyderabad, Chennai), AMD, Nvidia, Samsung SRI-B, Apple and Google silicon teams — standard-cell-based implementation, custom clock and memory cells, timing and power closure.
• Analog-mixed-signal and automotive semiconductor firms: Texas Instruments Bengaluru, NXP, Infineon, Renesas, ST — digital blocks inside power management ICs, motor controllers and AEC-Q100-qualified automotive MCUs.
• Memory and library/IP work: Micron (Hyderabad), Synopsys and Cadence IP teams, Arm India — SRAM compilers, standard cell library characterisation, PHY and I/O cell design.
• Strategic and public sector: SCL Mohali (180 nm CMOS line), ISRO/DRDO ASICs, BEL, C-DAC's VEGA and SHAKTI/AJIT processor efforts out of IIT Madras and IIT Bombay — taped out on Indian and foreign nodes.
• Services, verification and test: Tessolve, Sankalp Semiconductor, Einfochips, L&T Technology Services, Wipro and HCL VLSI practices — library QA, DFT, characterisation and silicon bring-up roles that need transistor-level intuition.
• Job roles: physical design engineer, standard cell/custom circuit designer, STA engineer, low-power architect, memory design engineer, and product/test engineering at the ATMP and OSAT units being set up under the India Semiconductor Mission.

Interview questions

• Q: Why does static CMOS dissipate almost no static power? A: The pull-up and pull-down networks are logical duals, so in any stable state one is fully off; only subthreshold and gate leakage flow.
• Q: Why is the pMOS made wider than the nMOS? A: Hole mobility is roughly 2-3× lower than electron mobility, so equal W/L gives weaker pMOS current; widening it equalises drive strength and centres the switching threshold.
• Q: Does the W/L ratio affect the logic levels of a CMOS inverter? A: No — CMOS is ratioless, V_OH = V_DD and V_OL = 0; the ratio only shifts V_M and the rise/fall delay balance.
• Q: Why is NAND preferred over NOR in CMOS? A: NOR stacks pMOS devices in series, requiring widths of 2k per device for equal speed, bloating area and input capacitance; NAND stacks the faster nMOS instead.
• Q: What limits the fan-in of a static CMOS gate? A: Series resistance and internal node capacitance both grow with fan-in, so delay rises roughly as the square of fan-in; beyond about four inputs gate trees are faster.
• Q: Why can't nMOS-only pass-transistor logic drive the next stage reliably? A: Its high output is only V_DD − V_tn, which partially turns on the following pMOS, causing static current and reduced noise margin; a level restorer or a transmission gate solves it.
• Q: Why can't plain dynamic gates be cascaded? A: During evaluate, a cascaded input starts high and may fall, by which time it may already have wrongly discharged the next dynamic node; domino adds a static inverter so inter-stage signals only rise.
• Q: What is charge sharing in dynamic logic and how is it reduced? A: The precharged output shares charge with internal PDN node capacitances during evaluate, drooping the output; reduced by precharging internal nodes, adding a keeper, or sizing the output node larger.
• Q: Can you fix a hold violation by reducing the clock frequency? A: No — hold is a same-edge, period-independent check; you must add delay to the short path or use a slower cell, or adjust skew.
• Q: Which power component dominates in advanced nodes and why? A: Leakage grows exponentially as V_t and oxide thickness shrink and can rival dynamic power, which is why multi-V_t cells, power gating and FinFET/GAA devices are used.
• Q: What is latch-up and how is it prevented in layout? A: Triggering of the parasitic well-substrate SCR that shorts V_DD to ground; prevented by abundant well and substrate taps, guard rings, epitaxial substrates and layout spacing rules.
• Q: What decides read stability versus writeability in a 6T SRAM cell? A: Read stability needs a large cell ratio (driver nMOS stronger than access nMOS) for adequate static noise margin; writeability needs a small pull-up ratio so the access device can overpower the cell pMOS — the two pull in opposite directions.
• Q: What is logical effort used for? A: Quick hand estimation and optimisation of path delay: d = gh + p, with minimum delay when stage efforts are equal at f = (GBH)^1/N.

Common mistakes

• Writing the pull-up network as a copy of the pull-down network instead of its dual (series ↔ parallel), or trying to realise non-inverting AND/OR directly in one static CMOS gate.
• Forgetting the series-stack width multiplication when sizing — leaving each nMOS in a 3-input NAND at unit width and then wondering why the gate is three times slow.
• Using the square-law saturation equation at short channel lengths, where velocity saturation makes current roughly linear in overdrive.
• Mixing up V_M (switching threshold of the gate) with V_t (device threshold), and ignoring the body effect on stacked or pass-transistor devices.
• Computing dynamic power as C V_DD² f without the activity factor α, or double-counting (the full CV²f is per complete 0→1→0 cycle, with one capacitor charge per rising edge).
• Claiming hold violations can be cured by lowering the frequency, or omitting clock skew from both setup and hold checks.
• Assuming dynamic/domino logic is always faster — ignoring clock power, keeper overhead, noise sensitivity and the inverting-function restriction.
• Drawing stick diagrams with broken diffusion strips because no common Euler path was found for the PUN and PDN.

Related topics

VLSI design flow · Design verification and UVM basics · Semiconductor fabrication and packaging · Analog IC design basics · Digital electronics and logic design · Computer architecture and memory systems