VLSI design flow

Electronics and Communication Engineering (B.E./B.Tech) · VLSI and semiconductors · free study notes for exams, placements and interviews

In short

VLSI design flow is the ordered sequence of steps that converts a chip specification into manufacturable layout data (GDSII/OASIS) sent to a foundry, and then into tested silicon. It exists because a modern SoC has billions of transistors that no human can draw by hand, so the design is captured as behaviour (RTL), mapped automatically to gates, then to geometry, with verification and timing checks at every stage. It is a guaranteed question area in GATE EC/EE (digital design, CMOS), university VLSI papers (design flow, Y-chart, design styles), and the first screening round at Intel, Qualcomm, Nvidia, AMD, Synopsys, Cadence, Siemens EDA, Texas Instruments, Samsung, Micron, Microchip, Bosch, Tessolve, Sankalp, SmartSoC, ISRO/SCL Mohali and C-DAC. India's Semiconductor Mission (ISM, 2021) and the Chips-to-Startup/ DLI schemes have made flow literacy a hiring baseline, since most Indian VLSI jobs are front-end/back-end design services rather than fabrication.

Explained

Abstraction levels and the Y-chart

Design abstraction hides detail to manage complexity: System → Algorithm → RTL (register transfer) → Logic/gate → Circuit/transistor → Layout/geometry. Each *higher* level has fewer objects but less accuracy.
Gajski-Kuhn Y-chart describes any design by three axes radiating from a centre: Behavioural (what it does), Structural (what it is made of), Physical/Geometrical (where things sit). Concentric rings are the abstraction levels.
Design = a spiral on the Y-chart: behaviour → structure (synthesis) → geometry (physical design), repeated at each lower ring. Moving behaviour→structure is *synthesis*; physical→structure is *extraction*; structure→behaviour is *analysis/abstraction*; staying on a ring while refining is *optimisation*.
Moore's law (transistor count per chip roughly doubles every 18-24 months) and Dennard scaling (now broken) are the economic driver: flows must be automated and hierarchical because gate counts grow faster than engineers.
Rent's rule I/O pins ∝ (gates)^p, p ≈ 0.5-0.7 - explains why partitioning and pin-count limits dominate early planning.

Design styles and their trade-offs

Full custom: every transistor and polygon drawn/sized by hand. Best area, speed, power; highest NRE and longest schedule. Used for analog blocks, SRAM bit-cells, I/O pads, high-speed SerDes.
Semi-custom / standard cell (ASIC): pre-characterised cells (NAND, flip-flop, buffer) of fixed height placed in rows; tools place and route. The mainstream digital flow.
Gate array / structured ASIC: wafers pre-fabricated up to transistors; only metal masks customised - lower NRE, faster turnaround, poorer density.
Programmable (FPGA/CPLD): SRAM-based LUTs, DSP slices, block RAM configured by a bitstream (CPLDs are smaller, flash-based macrocell arrays); zero mask cost, instant turnaround, but ~20-35× area for logic-only designs (≈18× when hard blocks are used), ~3-4× delay and higher static power per function.
Platform/SoC-based (IP reuse): integrate purchased or internal IP - CPU core (ARM, RISC-V), bus (AMBA AXI/AHB/APB), memory controller, PHY - as hard macros (fixed layout) or soft macros (synthesisable RTL).
MPW (multi-project wafer) shuttles share a mask set across designs; in India, SCL Mohali's 180 nm line and university MPW programmes under ISM/ C2S make small tapeouts affordable.

Front-end: specification to gate-level netlist

Specification & architecture: function, throughput, clock frequency, power budget, area/package, process node, interfaces, test strategy. Output is a micro-architecture and a verification plan.
High-level/behavioural modelling: C/C++/SystemC or MATLAB golden model; optional HLS (high-level synthesis) to RTL for dataflow blocks.
RTL coding: synthesisable Verilog/VHDL/SystemVerilog describing registers and the combinational logic between them. Coding style decides the hardware - blocking vs non-blocking assignment, complete sensitivity lists, no incomplete if in combinational blocks (avoids latches).
Functional verification: testbench simulation, assertions (SVA), code/functional coverage, constrained-random and formal property checking. Typically 50-70% of total project effort. Lint and CDC (clock-domain-crossing) checks run here.
Logic synthesis: RTL + target standard-cell library (.lib/Liberty) + constraints (SDC: clock period, input/output delays, false/multicycle paths, max fanout/transition) → gate-level netlist. Steps inside: translation to generic logic → technology-independent optimisation (Boolean, retiming, resource sharing) → technology mapping to real cells → incremental timing/area/power optimisation.
DFT insertion: scan chains replace flip-flops with scan flops, add ATPG patterns, BIST for memories (MBIST) and logic (LBIST), JTAG/boundary scan (IEEE 1149.1) for board test, compression (on-chip decompressor) to cut tester time.
Formal equivalence check (LEC): proves the gate netlist matches RTL after synthesis, DFT and later ECOs - required because simulation alone cannot cover all states.

Back-end: physical design (netlist to GDSII)

Partitioning & floorplanning: decide die size, aspect ratio, core/IO ring, macro (RAM/PLL) placement, block boundaries, pin assignment, power rings/straps, blockages, utilisation (typically 60-80%).
Power planning: VDD/VSS mesh sized for IR drop, decoupling capacitors, power gating cells (switch cells, isolation, level shifters, retention flops) driven by a UPF/CPF power-intent file for multi-voltage designs.
Placement: legal, non-overlapping positions for standard cells in rows minimising wirelength, congestion and timing cost; includes high-fanout net synthesis and physical-aware optimisation.
CTS (clock tree synthesis): build buffered clock distribution (H-tree, mesh, multi-source) to meet skew, latency and insertion-delay targets; clock usually consumes 20-40% of dynamic power.
Routing: global routing assigns nets to regions/metal layers, then detailed routing draws actual wires on the layer stack (M1 up); search-and-repair fixes shorts/opens; antenna, double-via and metal-fill rules applied.
Parasitic extraction (RC) → SPEF, then STA with real delays, signal-integrity (crosstalk) analysis, IR-drop/EM analysis, ECO fixes.
Physical verification / sign-off: DRC (does layout obey foundry geometry rules?), LVS (does layout's extracted netlist match the schematic/netlist?), ERC/antenna, DFM checks (CMP density, litho hotspots, OPC-friendliness), and final GDSII/OASIS + tapeout checklist.
Mask making and fabrication at the foundry, then wafer sort, packaging, final test, characterisation, qualification (JEDEC/AEC-Q100 for automotive), and production ramp. A silicon bug needing a metal-only or all-layer respin costs crores at advanced nodes - hence the verification emphasis.

Timing, constraints and sign-off checks

Setup check: data must arrive before the capture clock edge; hold check: data must stay stable after it. Setup fails are fixed by shorter logic/upsizing/retiming; hold fails by adding buffers/delay cells.
STA is static - it checks every path across all corners without vectors. PVT corners (process fast/slow, voltage ±10%, temperature −40 to 125 °C) and MMMC (multi-mode multi-corner) runs cover functional/test/low-power modes.
OCV/AOCV/POCV and derates model on-chip variation; CRPR removes pessimism on common clock paths.
Sign-off set: STA (setup, hold, transition, capacitance, clock quality), power (static + dynamic), IR/EM, SI/crosstalk, DRC/LVS/antenna, LEC, DFT coverage (typically >98% stuck-at target), reliability (ESD, latch-up).
Design closure is the iterative loop; a late timing/congestion failure forces a loop back to floorplan or even RTL - the single most common schedule risk.

FPGA flow, EDA tools and the Indian ecosystem

FPGA flow: RTL → synthesis → translate/map → place & route → timing analysis → bitstream → device programming (Xilinx/AMD Vivado, Intel Quartus, Lattice Radiant, open-source Yosys + nextpnr). No DRC/LVS/mask steps; prototyping and emulation on FPGA validate SoC RTL before tapeout.
Tool vendors: Synopsys (VCS, Design Compiler, Fusion Compiler, PrimeTime, IC Compiler II), Cadence (Xcelium, Genus, Innovus, Tempus, Virtuoso), Siemens EDA/Mentor (Questa, Calibre, Tessent). Foundry PDK (process design kit) supplies device models, Liberty, LEF/DEF, tech files and DRC decks under NDA.
Standards/formats: Verilog IEEE 1364, VHDL IEEE 1076, SystemVerilog IEEE 1800, UPF IEEE 1801, JTAG IEEE 1149.1, SDF, SPEF, LEF/DEF, GDSII/OASIS, Liberty.
India: ~20% of the world's chip design engineers work in India; design centres in Bengaluru, Hyderabad, Noida, Pune, Ahmedabad. Government levers - India Semiconductor Mission, Design Linked Incentive (DLI) scheme, Chips-to-Startup (C2S) giving colleges EDA tools and SCL/ foundry MPW access; the Micron ATMP unit at Sanand and Tata-PSMC fab at Dholera are building domestic manufacturing (status and incentive percentages change - verify current scheme terms).
Design-services model: most Indian engineers work as front-end (RTL/verification) or back-end (PD/STA/DFT) specialists for global product companies or service firms (Wipro, LTTS, Tata Elxsi, Sasken, HCLTech, Tessolve, SmartSoC, Sankalp, Mirafra).

Key points

VLSI design flow - specification → RTL → synthesis → physical design → sign-off → GDSII → fab → test.
Y-chart - behavioural, structural and physical domains × abstraction rings; synthesis moves behaviour to structure.
RTL - cycle-accurate description of registers and the logic between them; the hand-off point between front- and back-end.
Logic synthesis - needs RTL + Liberty library + SDC constraints; unconstrained synthesis produces unusable timing.
SDC - defines clocks, I/O delays, exceptions; it is the contract between design intent and the tools.
Netlist - gate-level instance-and-net list; verified against RTL by formal equivalence rather than resimulation.
DFT - scan chains + ATPG + MBIST + JTAG, inserted before physical design because it changes the netlist.
Floorplan - fixes die area, macro placement, power grid; a bad floorplan cannot be rescued by routing.
CTS - minimises skew and insertion delay; done after placement, before routing.
STA - vectorless timing check across PVT corners; setup = early-enough data, hold = long-enough stability.
DRC vs LVS - DRC checks layout against foundry geometry rules; LVS checks layout connectivity against the netlist.
GDSII/OASIS - binary layout database handed to the mask shop; tapeout is the release milestone.
Design styles - full custom (best PPA, slowest) > standard cell > gate array > FPGA (fastest, least efficient).
FPGA vs ASIC - FPGA has zero NRE and instant respin; ASIC wins on unit cost, power and speed at volume.
PPA - power, performance, area: every flow decision is a trade-off among these plus cost and schedule.
Verification dominates - roughly 50-70% of effort; a missed bug means a respin costing crores and months.
Hard vs soft IP - hard macro is fixed layout (portable only within a node); soft IP is synthesisable RTL.
Front-end vs back-end roles - RTL/verification vs PD/STA/DFT; Indian hiring is explicitly split this way.

Formulas and examples

Dynamic power P_dyn = α · C_L · V_DD² · f — α = switching activity factor (0-1), C_L = switched capacitance (F), V_DD = supply voltage (V), f = clock frequency (Hz); answer in watts.
Short-circuit + leakage: P_total = α C V² f + V_DD · I_short + V_DD · I_leak (I_leak becomes comparable to dynamic power at ~65 nm and below).
Propagation delay (alpha-power / simple RC): t_pd ≈ C_L · V_DD / I_D ∝ C_L V_DD /[ (W/L) (V_DD − V_th)^α ]
Setup check: T_clk ≥ t_cq + t_logic(max) + t_setup + t_skew — T_clk = clock period, t_cq = clock-to-Q of launch flop, t_setup = capture flop setup time.
Hold check: t_cq + t_logic(min) ≥ t_hold + t_skew
Slack = Required arrival time − Actual arrival time (setup); positive slack = timing met. Setup slack = T_clk − (t_cq + t_logic + t_setup) with skew/uncertainty included.
Maximum frequency f_max = 1 / T_clk,min
Elmore/wire delay (distributed RC line of length L): t ≈ 0.38 R C L² (R, C per unit length) — why long nets are buffered.
Core area ≈ (gate count × area per gate) / utilisation; Die area = core + I/O ring + seal ring
Yield (Poisson/Murphy approx.): Y = e^−A·D or Y = [(1 − e^−A·D)/(A·D)]² — A = die area (cm²), D = defect density (defects/cm²)
Gross dies per wafer ≈ π(R − √A)² / A (R = wafer radius, A = die area, same units)
Cost per good die = (wafer cost) / (gross dies per wafer × yield)
Rent's rule: N_pins = k · N_gates^p, p ≈ 0.5-0.7

Example 1 - maximum clock frequency and slack. A path has t_cq = 0.12 ns, combinational logic delay 1.45 ns, setup time 0.08 ns, clock skew + uncertainty 0.15 ns.

T_clk,min = 0.12 + 1.45 + 0.08 + 0.15 = 1.80 ns → f_max = 1/1.80 ns = 555.6 MHz.
If the design must run at 500 MHz (T_clk = 2.00 ns), setup slack = 2.00 − 1.80 = +0.20 ns → passes.
Hold check with minimum logic delay 0.10 ns and t_hold = 0.05 ns: 0.12 + 0.10 = 0.22 ns ≥ 0.05 + 0.15 = 0.20 ns → hold slack = +0.02 ns, marginal; CTS skew reduction or a delay cell is advisable.

Example 2 - dynamic power and voltage scaling. A block has C = 2.5 nF switched capacitance, α = 0.15, V_DD = 1.0 V, f = 500 MHz.

P = 0.15 × 2.5×10⁻⁹ × (1.0)² × 500×10⁶ = 0.15 × 2.5×10⁻⁹ × 5×10⁸ = 0.15 × 1.25 = 0.1875 W ≈ 188 mW.
Scale V_DD to 0.8 V and f to 400 MHz (DVFS): P = 0.15 × 2.5×10⁻⁹ × 0.64 × 4×10⁸ = 0.15 × 0.64 = 0.096 W ≈ 96 mW — a 20% voltage cut plus 20% frequency cut nearly halves dynamic power, the reason DVFS is standard in mobile SoCs.

Example 3 - die size, dies per wafer, yield and cost. 5 million gates, 1.2 µm² per gate (effective, at the chosen node), target utilisation 70%, 300 mm wafer, defect density D = 0.4/cm², wafer cost ₹4,00,000.

Core area = 5×10⁶ × 1.2 µm² / 0.70 = 6×10⁶/0.7 = 8.571×10⁶ µm² = 8.57 mm². Add 20% for I/O and seal ring → die ≈ 10.3 mm² = 0.103 cm²; side ≈ 3.21 mm.
Gross dies ≈ π(150 − √10.3)² / 10.3 = π(150 − 3.21)²/10.3 = π × 21,547/10.3 ≈ 6,571 dies.
Yield (Poisson) = e^{−0.103 × 0.4} = e^−0.0412 ≈ 0.960; Murphy model gives ≈ 0.960 as well at this small A·D.
Good dies ≈ 6,571 × 0.960 ≈ 6,308 → cost per good die ≈ ₹4,00,000/6,308 ≈ ₹63.4.
Quadruple the die to 41.2 mm² (0.412 cm²): gross dies ≈ π(150 − 6.42)²/41.2 ≈ π × 20,615/41.2 ≈ 1,572; Y = e^−0.165 ≈ 0.848; good dies ≈ 1,333 → ₹300 per die — nearly 5× the cost for 4× the area, which is why area discipline in floorplanning is a cost decision, not an aesthetic one.

Example 4 - FPGA prototype versus ASIC break-even. ASIC: NRE (masks + tools + engineering) ₹12 crore, unit cost ₹63. FPGA: NRE ₹40 lakh, unit cost ₹2,800.

Break-even volume V: 12,00,00,000 + 63V = 40,00,000 + 2,800V → 11,60,00,000 = 2,737V → V ≈ 42,382 units.
Below ~42,000 units the FPGA is cheaper; above it the ASIC wins, and the gap widens fast (at 1 million units: ASIC ≈ ₹18.3 crore vs FPGA ≈ ₹280.4 crore).

Example 5 - wire delay and buffering. A 4 mm global net with r = 0.1 Ω/µm and c = 0.2 fF/µm.

Unbuffered: t ≈ 0.38 × r c L² = 0.38 × 0.1 × 0.2×10⁻¹⁵ × (4,000)² = 0.38 × 0.1 × 0.2×10⁻¹⁵ × 1.6×10⁷ = 0.38 × 3.2×10⁻¹⁰ = 1.22×10⁻¹⁰ s ≈ 122 ps of pure RC (plus driver delay).
Split into 4 segments of 1 mm: each 0.38 × 0.1 × 0.2×10⁻¹⁵ × 10⁶ = 7.6 ps, total wire RC = 30.4 ps; adding 3 buffers at ~25 ps each gives ≈ 105 ps — the quadratic term is what buffering kills, and this is why CTS and HFNS exist.

Stage	Input	Main tool task	Output	Key check
Spec/architecture	Requirements	Micro-architecture, budgets	Spec + verification plan	Review sign-off
RTL design	Spec	Verilog/VHDL coding	Synthesisable RTL	Lint, CDC
Verification	RTL	Simulation, assertions, formal	Coverage closure	Functional coverage
Synthesis	RTL + .lib + SDC	Map to standard cells	Gate netlist, SDF	LEC, pre-layout STA
DFT	Netlist	Scan, ATPG, MBIST, JTAG	Scan-inserted netlist	Fault coverage
Floorplan/power	Netlist + LEF/DEF	Die, macros, power grid	DEF floorplan	IR drop, congestion
Placement	Floorplan	Cell placement, optimisation	Placed DB	Timing, congestion
CTS	Placed DB	Clock tree buffering	Clocked DB	Skew, latency
Routing	Clocked DB	Global + detailed routing	Routed DB	DRC, SI
Sign-off	Routed DB	Extraction, STA, PV	GDSII	DRC, LVS, STA, EM/IR

Aspect	FPGA	Standard-cell ASIC	Full custom
NRE / mask cost	None	High (crores at advanced nodes)	Highest
Time to first silicon	Minutes-hours	3-12 months	12-24 months
Unit cost at volume	High	Low	Lowest
Speed / power	Baseline	~3× faster, far lower power	Best
Respin cost	Re-download bitstream	New masks	New masks
Typical use	Prototyping, low volume, aerospace	Mainstream SoCs	Analog, SRAM, I/O, SerDes

Where it is used

Product semiconductor companies in India: Qualcomm (Bengaluru/Hyderabad - modem and SoC PD/STA), Intel, Nvidia, AMD, Texas Instruments, NXP, Infineon, Samsung SRI-B, Micron, Western Digital, Microchip, Analog Devices - roles in RTL design, verification, physical design, DFT, STA, library/characterisation.
EDA vendors: Synopsys, Cadence and Siemens EDA have large India R&D teams building the very tools in this flow - application engineer and R&D roles require flow fluency end to end.
Design-services and VLSI training firms: Tessolve, SmartSoC, Sankalp Semiconductor, Mirafra, Tata Elxsi, LTTS, Wipro, HCLTech - project-based front-end/back-end execution for global clients.
Government and strategic: SCL Mohali (180 nm fab plus design for ISRO/DRDO), C-DAC (VEGA RISC-V processors, AUM HPC chip), IIT Madras Shakti RISC-V cores - taped out through the C2S programme and SCL/ foundry MPWs.
Domestic manufacturing build-out: Micron ATMP (Sanand), Tata Electronics-PSMC fab (Dholera) and Tata OSAT (Jagiroad) extend the flow into packaging and test jobs in India.
Adjacent sectors: automotive electronics (AEC-Q100 qualified ICs at Bosch, Continental), defence/space ASICs, telecom (5G ORAN SoCs), consumer and IoT (RISC-V microcontrollers), and FPGA design in railways, radar and power electronics.

Interview questions

Q: Walk me through the RTL-to-GDSII flow. A: RTL coding and verification → logic synthesis with SDC and a standard-cell library → DFT insertion and equivalence check → floorplanning and power planning → placement → CTS → routing → extraction, STA and physical verification (DRC/LVS) → GDSII tapeout.
Q: What are the three inputs to logic synthesis? A: The synthesisable RTL, the technology library (Liberty .lib with cell timing/power) and the constraints file (SDC defining clocks, I/O delays and exceptions).
Q: Why is clock tree synthesis done after placement and not before? A: Clock buffer insertion and skew depend on the physical positions of the sequential cells, so placement must be known; doing it earlier would use wrong-length clock nets.
Q: Difference between DRC and LVS? A: DRC checks that the layout geometry obeys the foundry's spacing/width/enclosure rules; LVS extracts a netlist from the layout and compares connectivity and devices with the intended schematic/netlist.
Q: How do you fix a setup violation and a hold violation? A: Setup: upsize cells, reduce logic depth, use faster cells/lower V_th, restructure or retime, relax the clock; hold: insert buffers or delay cells on the short path, downsize cells, balance skew.
Q: Why is static timing analysis preferred over timing simulation? A: STA checks every path exhaustively without stimulus and runs orders of magnitude faster; simulation only covers the paths your vectors happen to exercise.
Q: What is slack and what does negative slack mean? A: Slack = required − arrival time; negative slack means the path misses its timing requirement and the design will fail at that frequency or corner.
Q: Why do we need formal equivalence checking if the RTL was already simulated? A: Synthesis, DFT insertion, scan stitching and ECOs change the netlist after simulation; LEC proves mathematically that the modified netlist is logically identical to the golden RTL for all input combinations.
Q: What is the difference between a hard macro and a soft macro? A: A hard macro is delivered as fixed layout (GDSII/LEF) with known timing and is node-specific; a soft macro is synthesisable RTL, portable across nodes but needing synthesis and timing closure.
Q: Why is DFT inserted before physical design? A: Scan flops, compressors and JTAG logic change the netlist, area and timing, so they must exist before floorplanning and placement; adding them later invalidates closure.
Q: Which is better, FPGA or ASIC? A: Neither absolutely - FPGAs win below roughly tens of thousands of units because they have no mask NRE and allow instant respins; ASICs win at volume on unit cost, power, speed and density.
Q: Why does a larger die cost disproportionately more? A: Fewer dies fit on a wafer and yield falls exponentially with area (Y ≈ e^−AD), so cost per good die rises faster than area.
Q: What does utilisation mean in a floorplan and what is a typical value? A: The fraction of core area occupied by cells; typically 60-80% at placement, leaving room for buffers, clock tree and routing - too high causes congestion and routing failure.

Common mistakes

Treating RTL as software: writing non-synthesisable constructs (delays, initial blocks, unbounded loops, division by a variable) and expecting the tool to produce hardware.
Confusing synthesis with physical design, or claiming "synthesis gives the layout" - synthesis gives a netlist; placement and routing give geometry.
Running synthesis with a missing or wrong SDC and then blaming the tool for timing failures; unconstrained paths are simply not optimised.
Forgetting clock skew, uncertainty and the launch flop's clock-to-Q in setup/hold calculations, or using setup time in the hold equation.
Believing hold violations can be fixed by slowing the clock - hold is clock-period independent and needs delay added to the data path.
Reversing DRC and LVS in interviews, or forgetting that antenna/ERC and DFM are also sign-off requirements.
Unit slips in power and cost arithmetic: fF vs pF, mW vs W, µm² vs mm², and forgetting that V_DD appears squared in dynamic power.
Quoting old node, incentive or scheme figures as current - India's semiconductor policy numbers and fab timelines keep changing and should be checked against the latest MeitY/ISM notification.