Semiconductor fabrication and packaging

In short

Semiconductor fabrication is the sequence of physical and chemical steps that turn a polished silicon wafer into thousands of working integrated circuits, and packaging is the set of steps that cuts, mounts, connects and seals each die so it can be soldered onto a board. Fabrication is where device physics, chemistry and precision optics meet manufacturing economics — yield, cost per die and reliability all come out of this stage. It is examined in GATE EC (and GATE IN, instrumentation) under "IC fabrication: oxidation, diffusion, ion implantation, photolithography, twin-tub CMOS", and in university papers on VLSI Technology. It matters practically because India's Semiconductor Mission (ISM, 2021) has funded fabs and ATMP/OSAT plants — Micron's ATMP in Sanand, the Tata-PSMC fab in Dholera, the Tata OSAT in Assam, CG Power-Renesas and Kaynes in Sanand — so fabrication and packaging roles now exist in India and not only abroad.

Explained

From sand to wafer: substrate preparation

• MGS (metallurgical grade silicon): quartzite reduced with carbon in an arc furnace, about 98% pure. Refined to EGS (electronic grade silicon), 99.9999999%+ (9N–11N), via trichlorosilane distillation and the Siemens process.
• Czochralski (CZ) growth: a seed crystal is dipped into molten silicon and pulled while rotating; dopant is added to the melt. Gives large diameters (200 mm, 300 mm) but higher oxygen content from the quartz crucible.
• Float zone (FZ) growth: a molten zone is swept along a rod by an RF coil with no crucible; very low oxygen and high resistivity — used for power devices and detectors, but costlier and limited in diameter.
• Segregation coefficient k₀ = Cs/Cl governs how dopant distributes between solid and liquid; k₀ < 1 for most dopants in silicon, so the tail of the ingot is more heavily doped (resistivity varies along the boule).
• Wafering: ingot is ground to diameter, flats or notches cut to mark orientation and type, sliced, lapped, chemically etched, and polished to a mirror finish by CMP. An epitaxial layer (lightly doped single crystal grown by CVD on the polished surface) is added for latch-up control and precise doping.
• Crystal orientation: (100) wafers for MOS (lower interface trap density, easier cleaving along 90° planes), (111) for bipolar.
• Clean room classes: ISO 14644-1 Class 1–5 in lithography bays (ISO 3 ≈ old Class 1, ISO 5 ≈ old Class 100); particles larger than about one-tenth of the feature size are killers.

Oxidation, diffusion and ion implantation

• Thermal oxidation: Si + O₂ → SiO₂ (dry, slow, dense, high quality — gate oxide) or Si + 2H₂O → SiO₂ + 2H₂ (wet, fast — thick field/masking oxide). Typically 900–1200 °C in a furnace or RTP tool.
• Deal-Grove model: oxide thickness follows x² + Ax = B(t + τ); initially linear-rate-limited (reaction at the interface), later parabolic (diffusion of oxidant through the growing oxide), so x ∝ √t for long times.
• Silicon is consumed: about 44% of the final oxide thickness comes from the wafer, so a step appears at a mask edge; LOCOS isolation shows lateral "bird's beak" encroachment, which is why STI (shallow trench isolation) replaced it below about 0.25 µm.
• Uses of SiO₂: gate dielectric, diffusion/implant mask, surface passivation, inter-level insulation, sacrificial layer. Below about 1.2 nm equivalent thickness, gate leakage forced a move to high-k dielectrics (HfO₂) with metal gates.
• Diffusion doping: dopant atoms move from high to low concentration at 900–1150 °C. Two cases — constant surface concentration (pre-deposition) gives an erfc profile; constant total dose (drive-in) gives a Gaussian profile. Diffusivity D = D₀ exp(−Ea/kT).
• Diffusion is isotropic (lateral spread under the mask) and cannot make shallow, precisely-dosed junctions; it is cheap and needs no implanter.
• Ion implantation: dopant ions accelerated to 5 keV–several MeV and fired into the wafer; dose is measured as the beam current integral, so doping is precise and reproducible, performed at low temperature, and self-aligned to the gate.
• Profile is approximately Gaussian about a projected range Rp with straggle ΔRp. Implantation causes lattice damage, removed by annealing (RTA/spike anneal, which also electrically activates the dopant with minimal diffusion).
• Channelling along crystal axes gives unwanted deep tails — avoided by tilting the wafer (about 7°) or using a screen oxide/pre-amorphisation.
• Common species: B/BF₂ (p-type), P, As (n-type); As is used for shallow source/drain because it is heavy and diffuses slowly.

Photolithography and pattern transfer

1. Clean and dehydrate the wafer; apply HMDS adhesion promoter.
2. Spin-coat photoresist (0.5–2 µm) — thickness varies as 1/√(spin speed).
3. Soft bake (prebake) to drive off solvent.
4. Align and expose through a mask/reticle. Positive resist: exposed region becomes soluble (pattern = mask pattern); negative resist: exposed region cross-links and stays. Positive resist gives better resolution and dominates.
5. Post-exposure bake and develop, then hard bake for etch/implant resistance.
6. Etch or implant through the resist opening; then strip the resist (plasma ashing or solvent).
7. Exposure systems: contact and proximity printing (cheap, mask damage, poor resolution) → projection step-and-repeat (stepper) and step-and-scan scanner with 4× reticle reduction.
8. Resolution R = k₁λ/NA and depth of focus DOF = k₂λ/NA² — pushing NA up buys resolution but loses depth of focus quadratically. Wavelengths progressed 436 nm (g-line), 365 nm (i-line), 248 nm (KrF), 193 nm (ArF), 193 nm immersion (water, effective NA up to about 1.35), and EUV at 13.5 nm.
9. Resolution enhancement: phase-shift masks, off-axis illumination, optical proximity correction (OPC), multiple patterning (LELE, SADP) when a single 193i exposure cannot reach the pitch.
10. Overlay/alignment accuracy must be a small fraction of the feature size; mask defects are repeated on every die, so reticles are inspected and pellicled.

Etching, deposition and interconnect

• Wet etching: chemical baths (HF for SiO₂, KOH/TMAH for silicon); high selectivity and throughput but mostly isotropic and poor for fine lines. KOH on silicon is anisotropic in the crystal sense (stops on (111) planes) — the basis of bulk MEMS.
• Dry (plasma) etching: RIE, ICP, DRIE. Combines chemical reaction with ion bombardment to give anisotropic, vertical profiles. Key metrics: etch rate, selectivity (film vs mask vs underlayer), anisotropy, uniformity, loading effect.
• Etch bias / undercut: the difference between the patterned resist dimension and the final etched dimension; critical dimension (CD) control is the whole game.
• Deposition — CVD: APCVD, LPCVD (good uniformity, batch, polysilicon and nitride), PECVD (low temperature, used over metal), ALD (one monolayer per cycle, conformal — high-k and barrier layers), and epitaxy (single-crystal).
• Deposition — PVD: evaporation (poor step coverage) and sputtering (better coverage, alloys, used for Al, Ti, TiN, Ta/TaN barriers).
• Metallisation: aluminium (with about 1% Si to stop junction spiking and 0.5% Cu to resist electromigration) patterned by etching; copper cannot be plasma-etched cleanly, so it uses the damascene/dual-damascene flow — etch trench and via in dielectric, deposit Ta/TaN barrier plus Cu seed, electroplate Cu, then CMP back to the dielectric.
• Silicide (TiSi₂, CoSi₂, NiSi) on gate and source/drain lowers sheet resistance; salicide is the self-aligned version.
• Low-k dielectrics (fluorinated/carbon-doped oxide, k down to about 2.5) reduce interconnect capacitance and RC delay. Contacts use tungsten plugs filled by CVD.

CMOS process flow, isolation and modern devices

• Twin-tub (twin-well) CMOS outline: lightly doped substrate (often p-epi on p+) → pad oxide/nitride → STI trench etch, oxide fill, CMP → n-well and p-well implants and drive-in → sacrificial oxide strip → gate oxide growth (or high-k by ALD) → polysilicon (or metal gate) deposition and patterning → LDD/halo implants → spacer formation (nitride) → heavy source/drain implants (self-aligned to gate + spacer) → RTA activation → silicide → contact/ILD → tungsten contacts → multi-level Cu damascene interconnect → passivation (nitride/oxide) and pad opening.
• Why self-aligned gate: the gate itself masks the source/drain implant, so overlap capacitance is minimal and no extra alignment step is needed — the single biggest reason polysilicon replaced aluminium gates.
• LDD (lightly doped drain) and halo implants control hot-carrier damage and short-channel effects; spacers set the LDD length.
• Latch-up (parasitic pnpn between well and substrate) is suppressed by epi on heavily doped substrate, guard rings and plentiful well/substrate contacts.
• Gate-first vs gate-last (replacement metal gate) are the two high-k metal gate integration schemes; gate-last avoids high-temperature damage to the metal work function.
• FinFET (22 nm onwards) and GAA nanosheet (2 nm class) use a 3D channel for electrostatic control; fins are formed by SADP/SAQP, not by direct lithography. Process nodes below about 22 nm are marketing names, not physical gate lengths.
• Process control: in-line metrology (ellipsometry for thickness, four-point probe for sheet resistance, SEM/scatterometry for CD), PCM/WAT test structures in the scribe line, SPC charts, and wafer sort/probe which marks or maps bad dies.
• Mask set cost is the dominant NRE; this is why MPW (multi-project wafer) shuttles exist for academic and start-up designs.

Yield, cost and economics

• Yield = good dies / total dies. Losses are random defects (particles — modelled by Poisson, Murphy or negative-binomial models), systematic/parametric loss, and edge die loss.
• Moore's law: transistor count per chip roughly doubles every two years — an economic observation, now sustained by 3D devices, advanced packaging and more mask layers rather than simple shrink. Dennard scaling (power density constant as dimensions shrink) broke down around 2005 because threshold voltage and leakage stopped scaling.
• Bigger wafers (300 mm, with 450 mm shelved) reduce cost per die through more dies per wafer and better edge utilisation.
• Fab vs fabless vs foundry vs OSAT: IDM (Intel, Samsung, Micron), fabless (Qualcomm, Nvidia, most Indian design centres), pure-play foundry (TSMC, UMC, GlobalFoundries), OSAT/ATMP (ASE, Amkor; Micron and Tata in India).
• Indian context: ISM under MeitY offers fiscal support to fabs, display fabs, compound-semiconductor/ATMP units and the DLI (Design Linked Incentive) scheme; SCL Mohali runs a legacy 180 nm line; C-DAC, SITAR, SAMEER and ISRO/SCL serve strategic needs. Chips for all practical purposes are covered by Indian customs/GST classification and, as electronic goods, by BIS registration (CRS) at the product level.

Packaging, assembly and test

• Functions of a package: mechanical protection, electrical connection to the board, heat removal, and protection from moisture and ions.
• Back-end flow: wafer sort/probe → wafer thinning (back-grind) → dicing (saw, laser or plasma) → die attach (epoxy or solder) → interconnect → encapsulation/moulding → marking → lead finish/trim-form or ball attach → final test → burn-in (where required) → tape and reel.
• Interconnect methods:
  • Wire bonding — thermosonic gold or copper ball-wedge bonds; cheapest per pin at low I/O, but peripheral-only so it scales poorly to high pin count; longest electrical path (inductance).
  • TAB (tape automated bonding) — bumps bonded to a patterned polyimide tape.
  • Flip chip — die is flipped onto solder bumps/C4 or copper pillars; shortest path, area array, best electrical and thermal performance, needs underfill for CTE mismatch.
• Package families: through-hole (DIP, PGA) → surface-mount peripheral-lead (SOIC, QFP, TQFP, SSOP) → area array (PGA, BGA, FBGA, LGA, QFN) → chip-scale (WLCSP, package area ≤ 1.2× die area) → SiP/MCM, PoP (package-on-package, used in mobile SoC + LPDDR), 2.5D interposer (silicon interposer with TSVs, as in HBM-attached GPUs), 3D stacking with TSVs, and chiplets joined by standard die-to-die links such as UCIe.
• Thermal path: junction-to-case/junction-to-ambient resistances in series; heat spreaders, exposed pads, thermal vias, TIM, heat sinks. θJA is board- and airflow-dependent, so datasheet values are reference conditions only.
• Reliability and failure modes: CTE mismatch causing solder fatigue, popcorning of moisture-sensitive packages during reflow (hence MSL ratings and bake, per J-STD-020/033), electromigration, wire sweep, delamination, whisker growth on pure tin, alpha-particle soft errors.
• Qualification standards: JEDEC JESD22 series (temperature cycling, HAST, HTOL), AEC-Q100 for automotive grade, MIL-STD-883 for military; IPC standards govern board assembly. India's E-Waste (Management) Rules, 2022 and RoHS limits under those Rules restrict lead, mercury, cadmium and hexavalent chromium — the reason for lead-free SAC solder and higher reflow temperatures.
• ESD and handling: packaged devices are classified by HBM/CDM levels; ESD-safe handling per IEC 61340-5-1 / ANSI-ESD S20.20 is mandatory on assembly lines.

Key points

• Czochralski vs float zone — CZ gives large, cheap wafers with oxygen; FZ gives high-purity, high-resistivity wafers for power devices.
• (100) orientation - standard for MOS because of lower interface trap density; (111) for bipolar.
• Dry oxidation - slow but dense and clean, used for gate oxide; wet oxidation fast, for thick masking oxide.
• Deal-Grove - linear growth for thin oxides, parabolic (x ∝ √t) for thick; 44% of oxide thickness is consumed silicon.
• Pre-deposition vs drive-in - erfc profile at constant surface concentration, Gaussian profile at constant dose.
• Ion implantation - precise dose, low temperature, shallow and self-aligned; needs anneal to repair damage and activate dopant.
• Channelling - deep dopant tail along crystal axes; avoided by 7° tilt or screen oxide.
• Positive resist - exposed area dissolves, better resolution; negative resist - exposed area hardens.
• R = k₁λ/NA - resolution improves with shorter λ and larger NA, but DOF falls as 1/NA².
• Wet etch - isotropic, selective, cheap; dry/RIE etch - anisotropic, vertical sidewalls, essential for fine geometry.
• LPCVD/PECVD/ALD - uniformity, low temperature, and monolayer conformality respectively.
• Dual damascene - the only practical way to pattern copper interconnect; relies on CMP.
• Self-aligned polysilicon gate - gate masks the source/drain implant, minimising overlap capacitance.
• STI replaced LOCOS - no bird's beak, tighter isolation pitch, planar surface for lithography.
• Latch-up - parasitic pnpn turn-on; prevented by epi substrate, guard rings and dense well contacts.
• Yield - falls exponentially with die area × defect density; drives the push for chiplets over huge monolithic dies.
• Flip chip vs wire bond - area array with short, low-inductance paths versus cheap peripheral bonding.
• Advanced packaging - WLCSP, PoP, 2.5D interposers, TSV 3D stacks and chiplets extend scaling when lithography cannot.
• ISM and ATMP - India's current entry point is assembly, test, marking and packaging plus legacy-node fabs, not leading-edge logic.

Formulas and examples

Example 1 — Wet oxidation time (Deal-Grove). For wet oxidation at 1000 °C take B = 0.287 µm²/h and B/A = 0.41 µm/h, starting from a bare wafer (τ ≈ 0). Target x = 0.5 µm. A = B/(B/A) = 0.287/0.41 = 0.700 µm. x² + Ax = B·t → (0.25) + (0.700 × 0.5) = 0.25 + 0.350 = 0.600 = 0.287 t. t = 0.600/0.287 = 2.09 h ≈ 125 minutes. Silicon consumed = 0.44 × 0.5 = 0.22 µm, so the oxide surface sits 0.5 − 0.22 = 0.28 µm above the original surface. Check the thick-film approximation: √(Bt) = √(0.287 × 2.09) = 0.775 µm — far from 0.5 µm, so this growth is still mixed linear-parabolic and the full quadratic was necessary.

Example 2 — Implant dose and peak concentration. A boron implant uses a 2 mA beam of singly charged ions for 30 s over a 300 mm wafer (area = π × 15² = 706.9 cm²). Q = I·t/(q·A) = (2×10⁻³ × 30)/(1.6×10⁻¹⁹ × 706.9) = 0.06/(1.131×10⁻¹⁶) = 5.3×10¹⁴ ions/cm². If Rp = 0.3 µm and ΔRp = 0.07 µm = 7×10⁻⁶ cm: Npeak = 0.4 Q/ΔRp = 0.4 × 5.3×10¹⁴/7×10⁻⁶ ≈ 3.0×10¹⁹ cm⁻³, located 0.3 µm below the surface.

Example 3 — Lithography resolution and depth of focus. With k₁ = 0.4, k₂ = 0.5:

• ArF dry, λ = 193 nm, NA = 0.93: R = 0.4 × 193/0.93 = 83 nm; DOF = 0.5 × 193/0.93² = 96.5/0.865 = 112 nm.
• ArF immersion, NA = 1.35: R = 0.4 × 193/1.35 = 57 nm; DOF = 96.5/1.8225 = 53 nm.
• EUV, λ = 13.5 nm, NA = 0.33: R = 0.4 × 13.5/0.33 = 16 nm; DOF = 6.75/0.1089 = 62 nm.

Immersion shrinks the printable feature by about 30% but more than halves the focus window — hence tight wafer flatness and focus control; EUV regains resolution at a modest NA.

Example 4 — Dies per wafer, yield and cost per good die. A 10 mm × 10 mm die (S = 1.0 cm²) on a 300 mm wafer with 3 mm edge exclusion: First term = π(15 − 0.3)²/1.0 = π × 216.09 = 678.9. Second term = π(30 − 0.6)/√2 = π × 29.4/1.4142 = 92.36/1.4142 = 65.3. N ≈ 678.9 − 65.3 = 614 dies. With D₀ = 0.5 defects/cm²: Poisson Y = e^−0.5 = 0.607; Murphy Y = [(1 − e^−0.5)/0.5]² = (0.3935/0.5)² = 0.787² = 0.619. Good dies (Poisson) = 614 × 0.607 ≈ 373. At a wafer cost of ₹4,50,000, cost per good die = 4,50,000/373 ≈ ₹1,206. Halving the die to 0.5 cm²: N ≈ π × 216.09/0.5 − π × 29.4/√1.0 = 1357.8 − 92.4 = 1265; Y = e^−0.25 = 0.779; good dies ≈ 985 → ₹457 per good die — area, not just count, drives cost.

Example 5 — Package thermal limit. A QFN device dissipates 1.8 W with θJA = 32 °C/W in still air at TA = 55 °C. TJ = 55 + 32 × 1.8 = 55 + 57.6 = 112.6 °C — within a 125 °C limit, with 12.4 °C margin. In a 70 °C enclosure: TJ = 70 + 57.6 = 127.6 °C — over limit. Maximum allowed dissipation = (125 − 70)/32 = 1.72 W, or switch to a package/board with θJA ≤ (125 − 70)/1.8 = 30.6 °C/W (more thermal vias or a copper pour under the exposed pad).

Where it is used

• Fabs and ATMP/OSAT plants in India: Micron's assembly-test plant at Sanand, the Tata Electronics-PSMC fab at Dholera, Tata's OSAT at Jagiroad (Assam), CG Power-Renesas-Stars and Kaynes Semicon at Sanand; SCL Mohali for strategic 180 nm devices. Roles: process engineer, equipment/tool owner, yield engineer, test and packaging engineer.
• Process and equipment engineering: owning a module (litho, etch, diffusion, CMP) — recipe control, SPC, preventive maintenance, excursion analysis; equipment vendors (Applied Materials, Lam, ASML, Tokyo Electron) have India engineering and support teams.
• Packaging, test and board-level design: package selection for thermal and signal integrity, MSL/reflow profiles, DFM and DFT for ATE; relevant at Bosch, Continental, Tejas Networks, Bharat Electronics, HAL and the EMS houses (Dixon, Syrma SGS, Kaynes).
• Fabless design houses: Qualcomm, Nvidia, AMD, Intel, Texas Instruments, NXP, Samsung and Analog Devices design centres in Bengaluru, Hyderabad, Noida and Pune — designers must read PDKs, DRC rules, metal stacks and package parasitics that come from fabrication reality.
• MEMS, power and compound semiconductors: pressure and inertial sensors, SiC/GaN power devices and RF front-ends use the same unit processes with different materials; CDAC, IISc, IITs and SITAR run academic fabs and MPW shuttles.
• Reliability and qualification labs: JEDEC/AEC-Q100 stress testing, failure analysis with SEM, FIB, X-ray and decapsulation — in captive labs and at BIS/NABL-accredited test houses.

Interview questions

• Q: Why is dry oxidation used for the gate oxide and wet oxidation for field oxide? A: Dry oxide grows slowly but is denser with fewer defects and a better Si-SiO₂ interface, which the thin gate dielectric needs; wet oxidation is much faster and so is used where thickness matters more than quality.
• Q: Why did ion implantation largely replace diffusion for source/drain doping? A: Implantation gives precise, reproducible dose control, works at low temperature, makes shallow junctions, and is self-aligned to the gate with negligible lateral spread.
• Q: What is channelling and how is it avoided? A: Ions travelling along open crystal directions penetrate much deeper than expected, giving a deep profile tail; it is avoided by tilting the wafer about 7°, rotating it, or implanting through a screen oxide or pre-amorphised layer.
• Q: Why must implanted wafers be annealed? A: Implantation displaces lattice atoms and leaves the dopant interstitial and electrically inactive; annealing (typically RTA) repairs the damage and moves dopant onto substitutional sites, with minimal extra diffusion.
• Q: Difference between positive and negative photoresist? A: In positive resist the exposed region becomes soluble and is washed away, reproducing the mask opening; in negative resist the exposed region cross-links and remains. Positive resist gives better resolution and is standard in IC manufacture.
• Q: What limits lithography resolution, and what is the cost of using a higher NA? A: R = k₁λ/NA, so resolution improves with shorter wavelength and larger numerical aperture — but depth of focus falls as 1/NA², demanding extreme wafer flatness and focus control.
• Q: Why is copper interconnect made by damascene rather than by etching? A: Copper has no clean volatile plasma etch chemistry, so trenches and vias are etched into the dielectric, lined with a diffusion barrier, electroplated with copper, and planarised by CMP.
• Q: Why is a self-aligned polysilicon gate used instead of a metal gate in classic CMOS? A: Polysilicon withstands the high-temperature source/drain anneal, so the gate can be patterned first and then mask the implant — eliminating gate-to-source/drain overlap capacitance and one critical alignment step.
• Q: What is latch-up and how does the process prevent it? A: Triggering of the parasitic pnpn path formed by the n-well, p-substrate and the source diffusions, which short-circuits supply to ground; lightly doped epitaxy on a heavily doped substrate, guard rings and plentiful well/substrate taps lower the parasitic resistances below the trigger point.
• Q: Why did STI replace LOCOS? A: LOCOS consumes lateral area through bird's-beak encroachment and leaves a non-planar surface; trench isolation is compact, vertical and planar after CMP, which lithography at fine nodes requires.
• Q: How does die area affect cost per good chip? A: Doubly — fewer dies fit per wafer and yield falls roughly as exp(−A·D₀), so cost per good die rises faster than area; this motivates splitting large designs into chiplets.
• Q: What is a flip-chip package and when is it preferred over wire bonding? A: The die is inverted onto an area array of solder bumps or copper pillars on the substrate; it is chosen for high pin count, low inductance power delivery, high-speed signalling and better heat removal, at higher cost and with underfill needed for CTE mismatch.
• Q: What is popcorning and how is it prevented? A: Moisture absorbed by the plastic moulding flashes to steam during reflow and cracks or delaminates the package; it is prevented by MSL classification, dry-pack with desiccant, and baking before assembly per the J-STD-020/033 limits.

Common mistakes

• Using the parabolic oxidation approximation x = √(Bt) for thin oxides, or forgetting τ when oxidising a wafer that already has an oxide.
• Ignoring the 0.44 silicon-consumption factor, then wondering why the oxide step height does not match the grown thickness.
• Swapping the erfc and Gaussian profiles — erfc for constant surface concentration (pre-deposition), Gaussian for constant dose (drive-in).
• Treating the implant peak as being at the surface instead of at the projected range Rp, or omitting the activation anneal from a process flow answer.
• Calling wet etching anisotropic because KOH etches silicon crystallographically — chemical isotropy and crystal-plane selectivity are different things.
• Mixing units in resolution and yield formulas: λ in nm with NA dimensionless is fine, but die area must be in cm² with D₀ in defects/cm².
• Writing a CMOS flow without the spacer, LDD and silicide steps, or placing the source/drain implant before gate patterning, which destroys self-alignment.
• Quoting a datasheet θJA as a fixed property — it is measured on a specified test board and airflow, and real board copper changes it substantially.

Related topics

VLSI design flow · CMOS digital IC design · MOSFET device physics and short-channel effects · Semiconductor physics: carriers, junctions and doping · Electronic product design and testing · Microelectronic reliability and failure analysis