8051 microcontroller

Electronics and Communication Engineering (B.E./B.Tech) · Microprocessors and embedded · free study notes for exams, placements and interviews

In short

The 8051 is an 8-bit CISC microcontroller introduced by Intel in 1980 that puts a CPU, ROM, RAM, timers, a serial port, four I/O ports and an interrupt system on one chip. Its register and memory map is small enough to be learnt completely, so Indian universities use it as the standard teaching microcontroller and lab kit (8051/AT89C51/AT89S52 trainer boards), and GATE EC/EE, ISRO, DRDO, BARC, BEL and ESE papers ask register-level questions on it almost every year. Placement interviews at embedded firms (Bosch, Continental, Tata Elxsi, KPIT, L&T Technology Services, HCL, Wipro VLSI/embedded, Mindtree) use 8051 questions to test whether a candidate actually understands registers, stacks, timers and interrupts rather than just library calls. Though new designs now use ARM Cortex-M or RISC-V, 8051 cores still ship inside USB controllers, smart cards, keyboard controllers, remote controls and ASIC/FPGA soft cores.

Explained

Architecture and on-chip resources

Core: 8-bit CPU, accumulator A, auxiliary register B (used only by MUL and DIV), 8-bit PSW, 8-bit stack pointer SP, 16-bit program counter PC, 16-bit data pointer DPTR (split as DPH:DPL).
Memory: classic 8051 has 4 KB on-chip ROM and 128 bytes on-chip RAM; the 8052 has 8 KB ROM and the AT89S52 8 KB flash, both with 256 bytes RAM. The 8031 has no internal ROM. External memory can extend to 64 KB program + 64 KB data.
Harvard-style separation: program and data memory are separate address spaces, so address 0000H in ROM and 00H in RAM are different locations. Program fetch uses PSEN; external data uses RD/WR with the MOVX instruction.
Peripherals: two 16-bit timers/counters (T0, T1; T2 added on 8052), one full-duplex UART, five interrupt sources, four 8-bit ports P0-P3, and an on-chip oscillator driven by a crystal (commonly 11.0592 MHz so that standard baud rates come out exact).
Clocking: one machine cycle = 12 oscillator periods (6 states × 2 phases). Most instructions take 1 or 2 machine cycles; MUL and DIV take 4.

Pin diagram and signals (40-pin DIP)

Port 0 (pins 32-39): dual purpose - lower address byte AD0-AD7 multiplexed with data when external memory is used. It is open-drain, so it needs external pull-up resistors (typically 10 kΩ) when used as general I/O.
Port 1 (1-8): plain 8-bit I/O with internal pull-ups.
Port 2 (21-28): general I/O, or upper address byte A8-A15 for external memory.
Port 3 (10-17): I/O with alternate functions - P3.0 RxD, P3.1 TxD, P3.2 INT0, P3.3 INT1, P3.4 T0, P3.5 T1, P3.6 WR, P3.7 RD.
Control pins: EA (pin 31) - tie high to run from internal ROM, tie low to force all fetches from external ROM; ALE (30) latches the low address byte from P0 into an external 74LS373/573 latch; PSEN (29) is the external code read strobe; RST (9) is an active-high reset needing at least 2 machine cycles high; XTAL1/XTAL2 (19, 18) for the crystal with two ~30 pF capacitors; Vcc (40) +5 V and Vss (20) ground.
Ports can sink more current than they source: each pin typically sinks a few mA, so LEDs and relays are driven in active-low (sink) configuration or through a ULN2803/transistor.

Internal RAM map and special function registers

00H-1FH: four register banks of R0-R7, selected by PSW bits RS1, RS0 (bank 0 = 00-07H, bank 1 = 08-0FH, bank 2 = 10-17H, bank 3 = 18-1FH).
20H-2FH: bit-addressable area - 16 bytes = 128 bits, addressed as bit 00H to 7FH (SETB 05H sets bit 5 of byte 20H).
30H-7FH: general-purpose scratchpad, which also holds the stack (SP resets to 07H, so the stack starts at 08H and would overwrite bank 1 - therefore good programs set SP to 2FH or higher).
80H-FFH: SFR space (direct addressing only). In an 8052 the same 80H-FFH *indirect* addresses reach the upper 128 bytes of RAM - direct vs indirect addressing distinguishes them.
Key SFRs: A (E0H), B (F0H), PSW (D0H), SP (81H), DPL (82H), DPH (83H), P0 (80H), P1 (90H), P2 (A0H), P3 (B0H), TCON (88H), TMOD (89H), TL0/TH0 (8AH/8CH), TL1/TH1 (8BH/8DH), SCON (98H), SBUF (99H), PCON (87H), IE (A8H), IP (B8H). SFRs whose address ends in 0H or 8H are bit addressable.
PSW bits: CY (carry, PSW.7), AC (auxiliary carry, used by DA A), F0 (user flag), RS1, RS0 (bank select), OV (overflow, signed arithmetic), — (reserved), P (parity of A, set if A has an odd number of 1s). Note there is no zero flag; branching on zero uses JZ/JNZ, which test A directly.

Instruction set and addressing modes

Addressing modes: immediate (MOV A,#55H), register (MOV A,R3), direct (MOV A,40H), register-indirect (MOV A,@R0 for internal RAM, MOVX A,@DPTR for external), indexed (MOVC A,@A+DPTR for look-up tables in ROM), and implied/bit (SETB P1.0).
Groups: data transfer (MOV, MOVX, MOVC, PUSH, POP, XCH, XCHD), arithmetic (ADD, ADDC, SUBB, INC, DEC, MUL AB, DIV AB, DA A), logic (ANL, ORL, XRL, CLR, CPL, RL, RLC, RR, RRC, SWAP), Boolean/bit (SETB, CLR, CPL, MOV C,bit, ANL C,/bit, JB, JNB, JBC), and branching (LJMP, AJMP, SJMP, JMP @A+DPTR, LCALL, ACALL, RET, RETI, CJNE, DJNZ, JZ, JNZ, JC, JNC, NOP).
Boolean processor: the 8051 can test, set and clear individual bits in one instruction with the carry flag as a 1-bit accumulator - this is why it suits control and switching applications.
Only SUBB exists (subtract with borrow), so plain subtraction is done as CLR C followed by SUBB.
MUL AB puts the 16-bit product with the low byte in A and the high byte in B; DIV AB leaves the quotient in A and the remainder in B (OV is set if B = 0).
DA A adjusts the result of a BCD addition; SWAP A exchanges the nibbles of A (useful for packing BCD or hex-to-ASCII conversion).
Jump reach: SJMP and all conditional jumps are relative (−128 to +127 bytes); AJMP/ACALL reach within a 2 KB page; LJMP/LCALL reach the whole 64 KB.
Stack: grows upward; PUSH increments SP then writes, POP reads then decrements. CALL pushes the 16-bit return address (2 bytes); flags and the accumulator are not saved automatically - an ISR must push them itself.

Timers, serial port and interrupts (8051-specific registers)

TMOD (not bit addressable) is split into nibbles - high nibble for T1, low for T0 - each with GATE, C/T (0 = timer counting machine cycles, 1 = counter counting pulses on T0/T1 pin) and M1 M0 selecting the mode: 0 = 13-bit, 1 = 16-bit, 2 = 8-bit auto-reload (reload value kept in TH), 3 = split timer (T0 becomes two 8-bit timers).
TCON holds the run and flag bits TR0/TR1 (start), TF0/TF1 (overflow flags - cleared by hardware on entering the ISR, by software in polled mode), plus the external interrupt flags IE0/IE1 and edge/level selects IT0/IT1.
Serial port: SCON selects the mode (0 = shift register, 1 = 8-bit UART with variable baud rate, 2 and 3 = 9-bit), enables reception with REN and reports TI and RI. SBUF is physically two registers - writing it transmits, reading it fetches the received byte. Timer 1 mode 2 generates the baud rate; SMOD in PCON doubles it.
Interrupts: five sources with fixed vectors - IE0 external 0 at 0003H, TF0 at 000BH, IE1 external 1 at 0013H, TF1 at 001BH, serial RI/TI at 0023H (8052 adds TF2 at 002BH). Reset vectors to 0000H. Vectors are 8 bytes apart, so a longer ISR starts with an LJMP.
IE register: EA (global enable) must be set along with the individual bits EX0, ET0, EX1, ET1, ES. IP gives each source high or low priority; within the same priority the fixed polling order is INT0, TF0, INT1, TF1, serial.
RETI (not RET) must end an ISR because it clears the interrupt-in-progress latch that blocks same-level interrupts.
Power saving via PCON: IDL stops the CPU but keeps timers and interrupts alive; PD (power-down) stops the oscillator and only reset or (in some derivatives) an external interrupt wakes it.

Programming, tools and 8051 in practice

Assembly is still examined (ORG, END, EQU, DB, DW directives; A51/ASEM-51 assemblers). Embedded C with Keil C51 or SDCC is standard in industry and labs: #include <reg51.h>, sbit LED = P1^0;, bit, data, idata, xdata, code memory types, and void t0_isr(void) interrupt 1 for the timer-0 ISR (interrupt numbers 0-4 map to the five vectors).
Reset state: PC = 0000H, A = B = PSW = 00H, SP = 07H, DPTR = 0000H, all ports = FFH (so port pins idle high and read as inputs), IP and IE cleared, SBUF indeterminate. Internal RAM contents are not cleared by reset.
Family and derivatives: 8031 (ROM-less), 8751 (EPROM), AT89C51/AT89S52 (Atmel/Microchip flash, in-system programmable - the usual Indian lab part), P89V51RD2, Silicon Labs C8051Fxxx and Dallas DS89C4x0 (single-cycle cores, far faster at the same crystal), plus 8051 soft cores in FPGA designs.
Limitations: 8-bit data path, no hardware divide beyond 8-bit DIV AB, tiny RAM, 12-clock machine cycle in the original core, no on-chip ADC/PWM in the classic part, and 64 KB address space - which is why most new Indian product designs move to ARM Cortex-M.
Standards and safety practice: 8051 code in automotive or industrial products is written to MISRA C and tested per the applicable functional-safety process (ISO 26262 for automotive E/E systems, IEC 61508 for industrial); Indian equipment carrying an 8051 still needs BIS certification and CE/EMC-type compliance per the product standard, and electronics placed in the Indian market falls under the Compulsory Registration Scheme for notified products. The exact notified-product list and scheme details change, so check the current BIS/MeitY notification.

Key points

8051 core - 8-bit CISC microcontroller, 4 KB ROM, 128 B RAM, 2 timers, 1 UART, 4 ports, 5 interrupts, 40-pin DIP.
Machine cycle - 12 clock periods; at 12 MHz one machine cycle = 1 µs, which makes timer sums easy.
11.0592 MHz crystal - chosen because it divides exactly to standard baud rates (9600, 4800, 2400).
Harvard-style map - separate 64 KB code and 64 KB data spaces; MOVC reads code, MOVX reads external data.
EA pin - high for internal ROM, low to force external program memory (always low on the 8031).
ALE and PSEN - ALE latches the low address byte off port 0; PSEN strobes external code reads.
Port 0 is open-drain - needs external pull-ups as I/O; ports 1-3 have internal pull-ups.
Register banks - four banks of R0-R7 at 00H-1FH, selected by PSW RS1:RS0; fast context switching in ISRs.
Bit-addressable RAM - 20H-2FH gives 128 individually addressable bits (00H-7FH) plus bit-addressable SFRs.
Stack grows upward from SP = 07H after reset; relocate SP above the register banks before using the stack heavily.
PSW has no zero flag - flags are CY, AC, F0, RS1, RS0, OV and P (parity of A).
DPTR - the only 16-bit pointer; used for external RAM (MOVX @DPTR) and ROM tables (MOVC A,@A+DPTR).
MUL AB / DIV AB - product low in A, high in B; quotient in A, remainder in B.
TMOD mode 2 - 8-bit auto-reload, the mode used for UART baud generation and periodic ticks.
Interrupt vectors - 0003H, 000BH, 0013H, 001BH, 0023H, 8 bytes apart; ISR must end with RETI.
Default priority order - INT0 > TF0 > INT1 > TF1 > serial, modifiable only between two levels via IP.
SBUF is two registers - one for transmit, one for receive, at the same address.
Timers are up-counters - they overflow at FFFFH→0000H, so the initial value is loaded as 65536 − required count.

Formulas and examples

Machine cycle time Tmc = 12 / fosc (s); fosc = crystal frequency in Hz
Timer tick (mode 1, C/T = 0) = Tmc; maximum delay (mode 1) = 65536 × Tmc; (mode 2) = 256 × Tmc
Count to load (mode 1) = 65536 − (required delay / Tmc), written as THx:TLx in hex
Count to load (mode 2, auto-reload) = 256 − (required delay / Tmc), written into THx
UART baud rate (mode 1) = fosc / (12 × 32 × (256 − TH1)) with SMOD = 0; doubled when SMOD = 1
Equivalently baud = (Timer-1 overflow rate) / 32, overflow rate = fosc / (12 × (256 − TH1))
Instruction execution time = (number of machine cycles) × Tmc
Delay-loop time ≈ (loop body machine cycles) × (iterations) × Tmc

Example 1 - machine cycle and instruction timing. Crystal = 11.0592 MHz.

Tmc = 12 / 11.0592 MHz = 1.0851 µs (often quoted as 1.085 µs).
A 2-machine-cycle instruction such as LJMP takes 2 × 1.085 = 2.17 µs.
A DJNZ loop of 250 iterations with a 2-cycle body: 250 × 2 × 1.085 µs ≈ 542.5 µs.
At 12 MHz instead, Tmc = 12/12 MHz = 1.000 µs exactly - which is why exam problems usually state 12 MHz.

Example 2 - 20 ms delay with Timer 0, mode 1, fosc = 12 MHz.

Tmc = 1 µs, so required counts = 20 ms / 1 µs = 20,000.
Load value = 65536 − 20000 = 45536 = B1E0H, so TH0 = B1H, TL0 = E0H.
Code: MOV TMOD,#01H (T0, mode 1, timer) · MOV TH0,#0B1H · MOV TL0,#0E0H · SETB TR0 · JNB TF0,$ · CLR TR0 · CLR TF0.
Check: 45536 counts up to 65536 = 20,000 ticks × 1 µs = 20 ms. For 1 second, repeat this loop 50 times.

Example 3 - serial port at 9600 baud, 8-bit data, 1 stop bit, fosc = 11.0592 MHz.

Timer-1 overflow rate needed = 9600 × 32 = 307,200 Hz.
Timer input clock = 11.0592 MHz / 12 = 921,600 Hz.
256 − TH1 = 921600 / 307200 = 3, so TH1 = 253 = FDH.
Setup: MOV TMOD,#20H (T1 mode 2) · MOV TH1,#0FDH · MOV SCON,#50H (mode 1, REN = 1) · SETB TR1; send with MOV SBUF,A then JNB TI,$ / CLR TI.
With a 12 MHz crystal the same calculation gives 1,000,000/307,200 = 3.26 - not an integer, so the baud rate would be off by about 8.5%, beyond the ~±3% a UART tolerates. That is the whole reason for the 11.0592 MHz crystal.

Example 4 - arithmetic and flags. A = 9CH, R2 = 7BH; execute ADD A,R2.

9CH + 7BH = 117H → A = 17H, CY = 1.
Low nibbles: Ch + Bh = 17h > 0Fh, so AC = 1.
Signed view: 9CH = −100, 7BH = +123, result +23 fits in 8 bits, so OV = 0.
A = 17H = 0001 0111B has four 1s (even), so parity flag P = 0.
If instead A = 50H and R2 = 50H: result A = A0H, CY = 0, but signed +80 + 80 = +160 overflows, so OV = 1 - showing CY and OV are different things.

Example 5 - square-wave frequency on a port pin. Timer 0 in mode 2 with TH0 = 9CH, fosc = 12 MHz, the pin toggled in the ISR.

Reload counts = 256 − 9CH = 256 − 156 = 100 → one overflow every 100 µs.
Each overflow toggles the pin, so half-period = 100 µs, period = 200 µs → f = 5 kHz.
For a 1 kHz square wave in the same mode, half-period = 500 µs > 256 µs maximum, so mode 2 cannot do it directly - use mode 1 (load 65536 − 500 = 65036 = FE0CH) or count several mode-2 overflows.

Feature	8051 (classic)	8052 / AT89S52
On-chip code memory	4 KB ROM	8 KB (ROM on 8052, flash on AT89S52)
Internal RAM	128 bytes	256 bytes
Timers	T0, T1	T0, T1, T2 (with capture)
Interrupt sources	5	6
Programming	Mask ROM / EPROM	In-system serial (ISP)

Timer mode	Size	Reload	Typical use
0	13-bit	Manual	Legacy, rarely used
1	16-bit	Manual	Long single delays
2	8-bit	Automatic (from TH)	Baud rate, periodic tick
3	Split 8-bit + 8-bit (T0)	Manual	Extra timer when T1 is busy with UART

Where it is used

Teaching and labs: 8051/AT89C51 trainer kits in almost every Indian ECE/EEE lab; microcontroller practicals, mini-projects and university viva voce.
Cost-sensitive consumer and appliance control: remote controls, washing-machine and microwave controllers, electronic weighing scales, water-level controllers, and legacy energy-meter and inverter designs from Indian manufacturers.
Embedded ICs that contain an 8051 core: USB bridge chips, SIM and smart cards, keyboard/touch controllers, RF transceiver modules (several CC-series parts), and 8051 soft cores dropped into ASIC and FPGA designs.
Industrial and instrumentation: small PLC modules, process indicators, motor-control boards and legacy SCADA remote terminals still in service, where 8051 firmware maintenance is a real job.
Job roles: embedded firmware engineer, hardware test and validation engineer, application engineer at distributors, and firmware maintenance roles at BEL, ECIL, ISRO/DRDO labs and automotive Tier-1 suppliers in Pune, Bengaluru and Chennai.
Exams and recruitment tests: GATE EC/EE/IN, ISRO/DRDO/BARC scientist exams, ESE, BEL/HAL/NTPC and PSU written tests, and the register-level screening questions in embedded placement rounds.

Interview questions

Q: Why is the 8051 called a microcontroller and not a microprocessor? A: It integrates CPU, ROM, RAM, timers, serial port, I/O ports and an interrupt controller on one chip, so it can run a system on its own, whereas a microprocessor needs all of these externally.
Q: Why must port 0 have external pull-up resistors? A: Its outputs are open-drain (no internal pull-up transistor), so it can pull a line low but cannot drive a logic high without an external pull-up.
Q: What happens if the EA pin is left low? A: All program fetches go to external memory, so internal ROM is ignored - correct for an 8031, but it makes an 8051 appear dead if nothing is connected externally.
Q: What is the default value of SP and why change it? A: SP resets to 07H, so the first push writes to 08H, which is register bank 1; moving SP to 2FH or above protects the banks and the bit-addressable area.
Q: Why must an ISR end with RETI instead of RET? A: RETI also clears the internal interrupt-in-progress flag; with RET that flag stays set and interrupts of that priority are permanently blocked.
Q: Which registers are saved automatically on an interrupt? A: Only the 16-bit return address (PC) is pushed; A, PSW, DPTR and the working registers must be saved by the ISR or protected by switching register banks.
Q: Why is an 11.0592 MHz crystal so common? A: Divided by 12 and 32 it yields exact standard baud rates (9600, 4800, 2400; 19200 and 57600 need SMOD = 1, which makes the divisor 16); 12 MHz gives non-integer timer reload values and several percent baud error.
Q: Difference between MOV, MOVX and MOVC? A: MOV accesses internal RAM and SFRs, MOVX accesses external data memory via @DPTR or @R0/@R1, and MOVC reads code memory for look-up tables.
Q: How are the upper 128 bytes of RAM in an 8052 distinguished from the SFRs at the same addresses? A: By addressing mode - direct addressing of 80H-FFH reaches the SFRs, indirect addressing (@R0/@R1) reaches the upper RAM.
Q: What is the maximum delay from one 16-bit timer at 12 MHz, and how do you get one second? A: 65536 × 1 µs ≈ 65.5 ms; a one-second delay needs software counting of repeated overflows, for example 20 overflows of a 50 ms setting.
Q: What is the difference between the CY and OV flags? A: CY is the carry out of bit 7 for unsigned arithmetic; OV flags a sign error in signed two's-complement arithmetic (carry into bit 7 differing from carry out).
Q: How does the 8051 generate a PWM output when it has no PWM peripheral? A: In software - a timer interrupt sets the pin at the start of each period and clears it after the on-time count, or two reload values alternate; derivative parts add hardware PCA/PWM units.
Q: What is the Boolean processor and why does it matter? A: The bit-level instruction set with the carry flag as a 1-bit accumulator, letting single bits be set, cleared, tested and combined in one instruction - ideal for relay-logic style control.

Common mistakes

Loading the required count directly into a timer instead of 65536 − count (mode 1) or 256 − count (mode 2); 8051 timers count up to overflow.
Forgetting to clear TF or TI/RI in polled code, or clearing TF inside an ISR where hardware already did it (harmless for TF, but TI and RI must always be cleared in software).
Using the stack without moving SP above 07H, which silently corrupts register bank 1.
Setting only the individual interrupt enable bits and forgetting EA in IE, so nothing fires.
Treating the P flag as a zero flag, or expecting ADD to set a zero flag - the 8051 has none; use JZ/JNZ on A.
Writing a 2 KB-crossing jump with AJMP/ACALL or an out-of-range SJMP/conditional jump (relative range is only −128 to +127).
Confusing code and data address spaces - trying to write to a MOVC table, or using MOV instead of MOVX for external RAM.
Ignoring the fact that ISR vectors are only 8 bytes apart, so a long handler written in place overruns the next vector.