Embedded interfaces: UART, SPI and I2C

In short

UART, SPI and I2C are the three serial interfaces that connect a microcontroller to the world - a GPS module, a display, a flash chip, a sensor, a PC terminal. They differ in three things only: whether a clock line is shared (synchronous or asynchronous), how many devices can hang on the same wires, and how fast they go. These three protocols appear in almost every embedded interview in India (Bosch, Continental, Qualcomm, Texas Instruments, Tata Elxsi, L&T Technology Services, HCL, Wipro, Cyient, ISRO/DRDO/BEL, Mindteck) and are standard questions in university exams; in GATE EC they sit under Digital Circuits (microprocessor, memory and I/O interfacing). Expect to be asked not only the pinouts but the timing arithmetic - baud rate, bits per frame, bus throughput - and the failure modes.

Explained

1. Serial basics and the vocabulary

• Serial vs parallel: serial sends bits one after another on one line; parallel sends 8 or 16 bits at once. Serial wins on pin count, cable cost, connector size and crosstalk - hence SATA, USB and PCIe replaced parallel buses.
• Simplex / half duplex / full duplex: one direction only; both directions but one at a time; both directions simultaneously. UART and SPI are full duplex; I2C is half duplex.
• Synchronous: a clock line is transmitted with the data (SPI, I2C), so the receiver samples exactly when told. Asynchronous: no clock line (UART); both ends must agree on baud rate beforehand and the receiver recovers timing from the start bit.
• Baud rate vs bit rate: baud = symbols per second; bit rate = bits per second. For two-level (binary) signalling they are numerically equal, which is why UART datasheets use them interchangeably - but in an exam, state the distinction.
• Master / slave (controller / target): the device that generates the clock and starts a transfer is the master. SPI and I2C have masters; UART is peer-to-peer with no master.
• Logic levels: TTL/CMOS serial is 0 V to 3.3 V or 5 V. RS-232 is ±3 to ±15 V with inverted logic, so a level shifter (MAX232, or a USB-UART bridge such as CP2102, FT232, CH340) sits between a microcontroller and a PC.

2. UART - asynchronous serial

• UART = Universal Asynchronous Receiver/Transmitter. USART adds an optional synchronous clock mode. Two wires carry data: TX and RX, cross-connected (TX of one to RX of the other) plus a common ground. No clock.
• Frame structure (in order on the wire):
  1. Start bit - one bit, logic 0 (line idles at logic 1), the falling edge that wakes the receiver.
  2. Data bits - 5 to 9, normally 8, sent LSB first.
  3. Parity bit - optional: none, even, odd, mark or space. Detects any odd number of bit errors; cannot correct, cannot see two flipped bits.
  4. Stop bit(s) - 1, 1.5 or 2 bits of logic 1, giving the receiver a guaranteed idle gap before the next start bit.
• So "9600 8N1" means 9,600 baud, 8 data bits, No parity, 1 stop bit = 10 bits per frame carrying 8 useful bits (80% efficiency).
• How the receiver recovers timing: the UART runs an internal clock at an oversampling factor of 16× (the 8051 samples at 16× in its asynchronous modes - the ÷32 in its baud formula is the baud divider, not the sampling factor; AVR uses 16× in normal mode and 8× in double-speed mode). On the falling edge of the start bit it counts 8 sub-clocks to the middle of the start bit, verifies it is still low (false-start rejection), then samples every 16 sub-clocks - i.e. at the centre of each bit. Many UARTs take 3 samples around the centre and majority-vote.
• Baud tolerance: sampling at the centre means the accumulated clock error at the last bit of a 10-bit frame must stay under half a bit, giving a practical limit of about ±2% mismatch between the two ends (±3-5% theoretical for 8N1, less with 9 data bits). This is why 11.0592 MHz crystals are used with 8051: it divides exactly to standard baud rates, whereas 12 MHz does not.
• Flow control: hardware RTS/CTS (request to send / clear to send) or software XON/XOFF (0x11/0x13 characters) stops a fast sender from overrunning a slow receiver.
• Errors reported in the status register:
  • Framing error - stop bit sampled as 0; usually a baud-rate mismatch or a broken frame.
  • Parity error - parity does not match.
  • Overrun error - a new byte arrived before software read the previous one (fix: interrupts, FIFO or DMA).
  • Break condition - line held low for longer than a whole frame.
• Standards built on UART framing: RS-232 (point-to-point, single-ended, ±12 V typical, up to about 15 m at 9,600 baud); RS-422 (differential, one driver many receivers, up to 1,200 m); RS-485 (differential, half duplex, multi-drop up to 32 unit loads, 1,200 m, 120 Ω termination) - the workhorse of Indian industrial systems and the physical layer under Modbus RTU. Note RS-232/422/485 are electrical standards (now TIA/EIA documents); UART is the on-chip framing engine.
• Pros: only two wires, no clock, works over long distance with RS-485 drivers, universally supported. Cons: both ends need accurate clocks, only two devices on plain TTL UART, no addressing, no built-in acknowledgement, slowest of the three.

3. SPI - Serial Peripheral Interface

• Invented by Motorola; a 4-wire, full-duplex, synchronous bus with no formal specification document, so vendors vary in detail.
• Lines:
  • SCLK - serial clock, always driven by the master.
  • MOSI - master out, slave in (newer naming: SDO/SDI or COPI).
  • MISO - master in, slave out (CIPO).
  • SS / CS / NSS - slave select, active low, one per slave.
• Operation: the master asserts CS low, then for every clock pulse one bit goes out on MOSI and one bit comes in on MISO simultaneously - it is a circular shift register of master and slave joined end to end. Reading a sensor therefore means writing a dummy byte to clock the answer out. MSB first is the usual default.
• The four SPI modes - set by CPOL (clock polarity: idle level of SCLK) and CPHA (clock phase: whether data is sampled on the first or second edge):

Mode 0 and mode 3 are the most common. A mismatched mode is the classic cause of data shifted by one bit or read as 0x00/0xFF.

• Multi-slave topologies:
  • Independent (star): SCLK, MOSI, MISO shared; one dedicated CS per slave. Needs n GPIOs for n slaves - the normal choice.
  • Daisy chain: MISO of one slave feeds MOSI of the next, a single CS for all; data ripples through, so n bytes must be clocked for n devices. Used for LED drivers and shift registers.
• Speed: limited by the slave, trace length and capacitance - typically 1-50 MHz; SD cards run at 25 MHz in SPI mode, QSPI/dual-SPI flash runs well above 100 MHz using 2 or 4 data lines.
• Pros: fastest of the three, full duplex, no addressing overhead, no start/stop/ACK overhead (100% payload efficiency), push-pull drivers so no pull-ups, no bus speed-vs-capacitance trade-off.
• Cons: 3 + n wires, no acknowledgement (master cannot tell whether a slave exists or is alive), no built-in error check, no defined frame length, short distance only (typically on-board, under ~30 cm), not hot-pluggable.

4. I2C - Inter-Integrated Circuit

• Developed by Philips (now NXP); a 2-wire, half-duplex, synchronous, multi-master, addressed bus. Also sold licence-free as TWI (Two Wire Interface) on Atmel/Microchip AVR parts.
• Lines: SDA (serial data) and SCL (serial clock), both open-drain/open-collector with external pull-up resistors to Vcc. A device can only pull the line low; the resistor pulls it high. This gives wired-AND behaviour - essential for acknowledgement, arbitration and clock stretching - and makes level translation between 3.3 V and 5 V parts easy.
• Bus conditions:
  • START: SDA falls while SCL is high. STOP: SDA rises while SCL is high. Repeated START (Sr): a new START without an intervening STOP - used to turn around from write to read while keeping the bus.
  • Data rule: SDA may change only while SCL is low; it must be stable while SCL is high. That is why a high-to-low transition on SDA during SCL high is unambiguously a START, never data.
• Transfer sequence (writing to a register of a slave):
  1. Master sends START.
  2. Master sends the 7-bit slave address + R/W̄ bit (0 = write) = one byte; slave pulls SDA low in the 9th clock as ACK.
  3. Master sends the register address byte; slave ACKs.
  4. Master sends the data byte(s), each ACKed.
  5. Master sends STOP. A read is: START, address+W, register pointer, repeated START, address+R, then the master clocks data out, ACKing each byte and sending NACK after the last byte, then STOP.
• Acknowledgement: after every 8 bits the transmitter releases SDA and the receiver pulls it low (ACK = 0) or leaves it high (NACK = 1). A NACK on the address byte means no such device - that is how an I2C bus scan works.
• Addressing: 7-bit gives 112 usable addresses (16 of the 128 are reserved - e.g. 0000 000 is the general call / START byte, 1111 0XX for 10-bit addressing, 1111 1XX for device ID). 10-bit addressing adds a second byte and extends the space to 1,024. Address clashes are the standard practical problem (two identical sensors) - solved with an address-select pin, an I2C multiplexer (TCA9548A) or a second bus.
• Speed modes (NXP UM10204 specification): Standard 100 kbit/s, Fast 400 kbit/s, Fast-mode Plus 1 Mbit/s, High-speed 3.4 Mbit/s, Ultra-Fast 5 Mbit/s (unidirectional, push-pull, no ACK). Total bus capacitance is limited to 400 pF, which caps the wire length to a few metres at best.
• Clock stretching: a slave that needs time holds SCL low after an ACK; the master, seeing the line still low, waits. Many hardware masters support it poorly - a frequent debugging surprise.
• Multi-master arbitration: masters may start together. Each monitors SDA while transmitting; a master that sends 1 but reads 0 has lost arbitration and withdraws silently. No data is corrupted because the lower address/data value wins - arbitration happens bit by bit and is non-destructive.
• Pull-up sizing: too large a resistor gives slow rising edges (RC) and failed timing; too small wastes current and may exceed the 3 mA sink rating. 4.7 kΩ at 100 kHz and 1-2.2 kΩ at 400 kHz are typical starting points.
• Pros: only 2 wires for many devices, built-in addressing and ACK, multi-master, hot-plug tolerant, standardised. Cons: slower than SPI, half duplex, heavy protocol overhead (a one-byte register write clocks 27 bits to move 8 - about 30% efficiency; 89% only on long bursts), needs pull-ups, open-drain limits speed, a stuck slave can hang the whole bus (recovery: clock out 9 pulses on SCL, then a STOP).
• SMBus is a stricter I2C derivative (timeouts, defined packet error checking) used for battery and power management; PMBus extends it.

5. Choosing between them, and related buses

• Distance: long cable → RS-485/Modbus over UART. On-board, many sensors, slow → I2C. On-board, high throughput (SD card, flash, display, ADC) → SPI.
• Pin budget: I2C is constant (2 lines) regardless of device count; SPI grows one line per device; UART grows two lines per link.
• Reliability needed: I2C's ACK tells the master the device responded; SPI tells you nothing, so SPI drivers usually read back a known ID register (the WHO_AM_I byte) to confirm presence.
• Other buses to name, not confuse: CAN (differential, multi-master, message-ID arbitration, automotive, 1 Mbit/s classic); LIN (single-wire UART-based, cheap automotive); 1-Wire (DS18B20 temperature sensor, one data line plus ground); USB; I2S (digital audio, not I2C).
• Debugging kit: a logic analyser or oscilloscope with protocol decode is the only honest way to debug these. Check in this order - ground connected, supply and logic levels, pull-ups present (I2C), correct mode/baud, correct address, scope the actual edges.

Key points

• UART - asynchronous, full duplex, 2 wires (TX, RX) + ground, no clock, point-to-point, no addressing.
• SPI - synchronous, full duplex, 4 wires (SCLK, MOSI, MISO, SS), master-slave, fastest, no ACK.
• I2C - synchronous, half duplex, 2 wires (SDA, SCL) + pull-ups, addressed, multi-master, ACK after every byte.
• UART frame - 1 start + 5-9 data (LSB first) + optional parity + 1/1.5/2 stop; 8N1 = 10 bits per byte.
• Oversampling - the UART samples at 16× the baud rate and reads each bit at its centre; mismatch must stay within about ±2%.
• 11.0592 MHz - the classic 8051 crystal because it divides exactly into standard baud rates.
• Framing error = bad stop bit (usually wrong baud); overrun = byte not read in time; parity error = odd number of flipped bits.
• RS-232 vs RS-485 - single-ended ±12 V, 15 m, two nodes vs differential, 1,200 m, 32 nodes, half duplex, 120 Ω terminated.
• CPOL/CPHA - four SPI modes; mode 0 (idle low, sample on rising edge) is the usual default.
• SPI is a shift-register exchange - one bit always goes out for every bit that comes in; reading needs a dummy write.
• Slave select is active low and must be released between transfers to reset the slave's bit counter.
• I2C START = SDA falls while SCL high; STOP = SDA rises while SCL high; data changes only when SCL is low.
• ACK - receiver pulls SDA low on the 9th clock; a NACK on the address byte means the device is absent.
• Clock stretching - a slave holds SCL low to buy time; the master must tolerate it.
• Arbitration - a multi-master I2C loser detects 1-sent-but-0-read and backs off; non-destructive.
• 7-bit addressing gives 112 usable addresses; address clashes are solved with address pins or a TCA9548A multiplexer.
• Open-drain + pull-up makes wired-AND possible and permits mixed 3.3 V/5 V devices; it also limits speed via RC rise time.
• Efficiency - SPI 100% payload, UART 8N1 80%, I2C about 30% for a one-byte register write (8 payload bits in 27 clocked bits), rising to 89% (8 of 9) on a long burst.

Formulas and examples

Example 1 - UART frame time and throughput. A GPS module streams at 9,600 baud, 8N1.

• Bits per frame N = 1 + 8 + 0 + 1 = 10.
• Bit time = 1/9,600 = 104.17 µs; frame time = 10 × 104.17 µs = 1.0417 ms per byte.
• Maximum data throughput = 9,600 × 8/10 = 7,680 bit/s = 960 bytes/s.
• A 70-character NMEA sentence takes 70 × 1.0417 ms ≈ 72.9 ms, so at most about 13 such sentences per second - which is why a 1 Hz GPS fix fits easily at 9,600 baud, but a 10 Hz fix or a dense multi-constellation stream needs 38,400 or 115,200 baud.
• If parity and 2 stop bits are added (8E2), N = 12, frame time = 1.25 ms, throughput = 9,600 × 8/12 = 800 bytes/s - a 17% loss.

Example 2 - 8051 baud rate reload value. Find TH1 for 9,600 baud with f_osc = 11.0592 MHz, SMOD = 0.

• Timer 1 overflow rate needed = 32 × 9,600 = 307,200 Hz (mode 1 uses a divide-by-32 of the timer overflow).
• Timer clock = f_osc/12 = 11.0592 × 10⁶/12 = 921,600 Hz.
• Divisor = 921,600/307,200 = 3 → TH1 = 256 − 3 = 253 = 0xFD. Error = 0%.
• Repeat with f_osc = 12 MHz: timer clock = 1,000,000 Hz; divisor = 1,000,000/307,200 = 3.26 → must round to 3, giving actual baud = 1,000,000/(32 × 3) = 10,417 baud. Error = (10,417 − 9,600)/9,600 = +8.5%, far beyond the ±2% budget - the link will fail with framing errors. That is the whole reason for the 11.0592 MHz crystal.

Example 3 - AVR UBRR and baud error. f_osc = 16 MHz, desired 115,200 baud, normal mode.

• UBRR = 16,000,000/(16 × 115,200) − 1 = 8.6806 − 1 = 7.68 → round to 8.
• Actual baud = 16,000,000/(16 × (8 + 1)) = 16,000,000/144 = 111,111 baud. Error = (111,111 − 115,200)/115,200 = −3.55% - marginal, and a known cause of garbage on 16 MHz Arduino boards at 115,200.
• With double-speed (U2X = 1): UBRR = 16,000,000/(8 × 115,200) − 1 = 17.36 − 1 = 16.36 → 16; actual = 16,000,000/(8 × 17) = 117,647 baud, error +2.12%. Better. With a 14.7456 MHz crystal, UBRR = 14,745,600/(16 × 115,200) − 1 = 8 − 1 = 7 exactly → 0% error.

Example 4 - I2C versus SPI time for the same job. Read 6 bytes (X, Y, Z accelerometer data) from an MPU-6000 (the MPU-6050 is the I2C-only version of the same part).

• I2C at 400 kHz: bytes on the wire = address+W, register pointer, then repeated START, address+R, 6 data bytes = 9 bytes × 9 clocks = 81 clocks, plus roughly 3 clock-times for START, Sr and STOP ≈ 84 clock periods. Time = 84/400,000 = 210 µs.
• SPI at 8 MHz: 1 command byte + 6 data bytes = 7 bytes × 8 = 56 clocks → 56/8,000,000 = 7 µs, plus CS setup. About 30 times faster.
• At a 1 kHz control loop (1,000 µs budget) the I2C read consumes 21% of the period; the SPI read, 0.7%. This is exactly why IMUs in drones and in automotive ESC units are wired on SPI.

Example 5 - I2C pull-up resistor. Fast mode, 400 kHz, V_cc = 3.3 V, measured bus capacitance C_b = 150 pF, t_r allowed = 300 ns, I_OL = 3 mA, V_OL(max) = 0.4 V.

• R_max = 300 × 10⁻⁹ / (0.8473 × 150 × 10⁻¹²) = 300 × 10⁻⁹ / (1.271 × 10⁻¹⁰) ≈ 2,360 Ω.
• R_min = (3.3 − 0.4)/0.003 = 967 Ω.
• So choose a standard value between them - 1.5 kΩ or 2.2 kΩ. The common 4.7 kΩ exceeds R_max here and would give rise times too slow for 400 kHz (it is fine at 100 kHz, where t_r allowed is 1,000 ns → R_max ≈ 7.9 kΩ).

/* Bare-metal shape of each - register names are device-specific */

/* UART, AVR, 8N1 */
void uart_init(uint32_t baud){
    uint16_t ubrr = F_CPU/(16UL*baud) - 1;   /* round: ((F_CPU+8UL*baud)/(16UL*baud))-1 */
    UBRR0H = ubrr >> 8;  UBRR0L = ubrr;
    UCSR0B = (1<<TXEN0)|(1<<RXEN0);
    UCSR0C = (1<<UCSZ01)|(1<<UCSZ00);        /* 8 data, 1 stop, no parity */
}
void uart_tx(uint8_t c){ while(!(UCSR0A & (1<<UDRE0))); UDR0 = c; }

/* SPI master: one function both writes and reads - full duplex */
uint8_t spi_xfer(uint8_t out){
    SPDR = out;
    while(!(SPSR & (1<<SPIF)));
    return SPDR;                              /* the byte clocked in */
}
/* read a register: CS low, send reg|0x80, send dummy, CS high */

/* I2C write of one register (polled, master mode) */
/* START -> addr<<1|0 -> reg -> data -> STOP, checking ACK at each step */

Where it is used

• Automotive electronics (Bosch, Continental, Visteon, Tata Elxsi, KPIT, Minda): I2C for EEPROMs and PMICs inside an ECU, SPI for IMUs and safety watchdog chips, UART/LIN for door and seat modules, CAN between ECUs - a standard interview sequence is "which bus for which signal, and why".
• Industrial automation and energy meters (L&T, Siemens India, Secure Meters, Genus, HPL): RS-485 + Modbus RTU over UART is the dominant field bus; smart meters under India's RDSS programme carry an RS-485 or optical UART port, and Indian meter standards sit in the IS 15959 / IS 16444 family (check the current revision before quoting a clause).
• Consumer and IoT products (Bharat FOTA/Jio modules, Tata Elxsi, HCL, Wipro, Mindteck): an ESP32 or STM32 talking I2C to a BME280 and OLED, SPI to an SD card or SX1278 LoRa radio, UART to a SIM800/Quectel GSM modem - the standard capstone and internship project stack.
• Space, defence and research (ISRO, DRDO, BEL, BHEL, SAMEER): SPI/I2C for on-board housekeeping sensors and SPI flash in payload electronics; design reviews focus on hot-plug behaviour, bus-hang recovery and EMI on long serial runs.
• Semiconductor and tooling roles (Qualcomm, TI India, NXP, Analog Devices, Synopsys, Cadence): writing and verifying UART/SPI/I2C controller IP in Verilog, running protocol-compliance verification IP, and writing the Linux kernel drivers (spi_sync(), i2c_smbus_*, /dev/ttyS*).
• Job roles: embedded firmware engineer, board-support/driver developer, hardware validation engineer, test and automation engineer, FPGA verification engineer - serial-protocol questions appear in nearly every one of these screens.

Interview questions

• Q: Why does UART need no clock line, and what does it cost? A: Both ends are pre-configured to the same baud rate and the receiver resynchronises on each start bit; the cost is a start and stop bit per byte (20% overhead) and a requirement that the two clocks match within roughly 2%.
• Q: Why is 11.0592 MHz used with the 8051? A: Dividing by 12 and 32 gives exactly 28,800 and from there integer divisors for 9,600, 4,800, 2,400 and so on; 12 MHz gives an 8.5% error at 9,600 baud, which causes framing errors.
• Q: What is a framing error and what usually causes it? A: The receiver sampled the stop-bit position as logic 0; the usual causes are a baud-rate mismatch, wrong number of data bits, noise, or a break condition on the line.
• Q: Why must I2C lines be open-drain with pull-ups? A: So multiple devices can share the line without contention - any device can pull low, nobody drives high - which is what makes ACK, clock stretching and arbitration possible, and allows mixed-voltage devices.
• Q: How does an I2C master know a device is present? A: It sends the address byte and checks the 9th clock; a low SDA is an ACK (device present), a high SDA is a NACK (no such device) - this is how a bus scan is written.
• Q: What is a repeated START and why is it needed? A: A START issued without a preceding STOP; it lets a master switch from writing a register pointer to reading data without releasing the bus, so another master cannot interleave a transfer.
• Q: What are CPOL and CPHA? A: Clock polarity (SCLK's idle level) and clock phase (whether the slave samples on the first or second clock edge); together they define the four SPI modes, and a mismatch corrupts every byte.
• Q: In SPI, how do you read without writing? A: You cannot - the bus is a shift-register exchange, so the master clocks out a dummy byte (often 0x00 or 0xFF) to shift the slave's data in.
• Q: SPI has no ACK; how do you verify a slave is working? A: Read a known constant - the device-ID or WHO_AM_I register - and compare it with the datasheet value; also check CS wiring and mode before blaming the slave.
• Q: What is clock stretching, and what goes wrong with it? A: A slave holds SCL low after an ACK to gain processing time; several hardware I2C masters (and bit-banged ones) handle it badly, causing timeouts or corrupted transfers.
• Q: Two identical I2C sensors, same fixed address - what do you do? A: Use the device's address-select pin or solder strap if it has one; otherwise put them on separate I2C buses or behind an I2C multiplexer such as the TCA9548A.
• Q: An I2C bus is stuck with SDA held low. How do you recover it? A: Toggle SCL up to nine times to let the slave finish its byte and release SDA, then issue a STOP; if that fails, power-cycle or reset the slave, and check whether a missed STOP or a reset mid-transfer caused it.
• Q: Which bus would you choose for a 50 cm cable to a temperature sensor in a factory panel? A: Not I2C or SPI - use RS-485/Modbus over UART (or a 1-Wire part for short runs); I2C's 400 pF capacitance limit and SPI's unterminated single-ended lines are not meant for cabling.

Common mistakes

• Forgetting the start and stop bits when computing byte time - using 8 bits per byte instead of 10 gives a 20% wrong answer.
• Writing TX to TX and RX to RX, or omitting the common ground - UART needs crossed data lines and a shared reference.
• Connecting a 5 V RS-232 port straight to a microcontroller pin: RS-232 swings to ±12 V and is inverted; a MAX232 or USB-UART bridge is mandatory.
• Omitting I2C pull-ups (nothing works) or keeping 4.7 kΩ at 400 kHz and 1 MHz (rise time too slow) - size them from t_r and C_b.
• Confusing the 7-bit address with the 8-bit written byte: an address of 0x68 is sent as 0xD0 for a write and 0xD1 for a read; datasheets and libraries disagree about which they quote.
• Leaving SPI slave select permanently low, or sharing one CS across two slaves - the slave's internal bit counter never resets and bytes shift out of alignment.
• Assuming SPI or I2C will tolerate a long cable, and ignoring that neither has error checking strong enough for a noisy field environment.
• Treating baud and bit rate as always identical, or claiming parity can correct errors - it only detects an odd number of flipped bits.

Related topics

Microcontroller peripherals: timers, ADC, PWM and interrupts · 8051 microcontroller · ARM and embedded C · Sensors and actuators for embedded systems · Internet of Things basics · PCB design, EMI and EMC