8085 and 8086 microprocessors

Electronics and Communication Engineering (B.E./B.Tech) · Microprocessors and embedded · free study notes for exams, placements and interviews

In short

The Intel 8085 is an 8-bit microprocessor (1976) with a 16-bit address bus, 64 KB memory space and a simple single-bus architecture; the Intel 8086 (1978) is a 16-bit processor with a 20-bit address bus, 1 MB memory space, segmented memory and a pipelined fetch-execute design. Both are studied as the canonical teaching models for how any CPU fetches, decodes and executes instructions, how buses and timing diagrams work, and how peripherals are interfaced. They carry heavy weight in university theory and lab exams, in GATE EC/EE/CS (addressing modes, physical address computation, instruction timing) and in entry-level embedded and VLSI interviews (Bosch, Continental, L&T Technology Services, Tata Elxsi, KPIT, HCL, Cyient, ISRO/DRDO/BEL technical rounds). The concepts — register sets, flags, stack, interrupts, memory mapping, bus cycles — transfer directly to every modern microcontroller and SoC.

Explained

8085 architecture and pins

8-bit data bus, 16-bit address bus → 64 KB (2¹⁶) memory; separate 256-byte I/O space (8-bit port address, 00H–FFH). Single +5 V supply, NMOS, 40-pin DIP.
Clock: on-chip clock generator with external crystal at 2 × operating frequency; a 6.144 MHz crystal gives a 3.072 MHz internal clock → T-state = 325.5 ns. Maximum rated 3 MHz (8085A); 8085AH-2 at 5 MHz.
Registers: accumulator A (8-bit), general-purpose B, C, D, E, H, L (usable as pairs BC, DE, HL — HL is the default memory pointer, M), SP (16-bit stack pointer), PC (16-bit program counter), plus temporary W, Z registers invisible to the programmer.
Flag register (5 flags in an 8-bit register): S (sign, bit 7), Z (zero, bit 6), AC (auxiliary carry, bit 4), P (parity — set for *even* parity, bit 2), CY (carry, bit 0). Bits 5, 3, 1 are undefined.
Multiplexed bus: AD0–AD7 carry the low address byte during T1 and data during T2–T3; A8–A15 carry the high byte throughout. ALE (address latch enable) high in T1 latches the low address into an external latch (74LS373) — this demultiplexing is the most-asked timing question.
Control and status: RD̄, WR̄, IO/M̄, S1, S0 define the machine cycle; READY (wait-state insertion), HOLD/HLDA (DMA), RESET IN̄/RESET OUT, SID/SOD (serial in/out, used by RIM/SIM).
Other blocks: ALU with the accumulator and temporary register, instruction register and decoder, timing-and-control unit, incrementer/decrementer address latch, interrupt control, serial I/O control.

8085 instruction cycle, machine cycles and timing

Hierarchy: instruction cycle = one or more machine cycles; machine cycle = 3 to 6 T-states (one clock period each).
Machine cycle types and their status lines:

Machine cycle	IO/M̄	S1	S0	T-states
Opcode fetch	0	1	1	4 (or 6)
Memory read	0	1	0	3
Memory write	0	0	1	3
I/O read	1	1	0	3
I/O write	1	0	1	3
INTR acknowledge	1	1	1	6 (or 12)
Halt / bus idle	Z	0	0	—

Opcode fetch: T1 — address out + ALE; T2 — RD̄ low, memory drives data; T3 — data latched into IR; T4 (and T5, T6 if needed) — decode/execute for multi-byte-register operations such as CALL, PUSH, INX.
Instructions take 1 to 5 machine cycles and 4 to 18 T-states (e.g. MOV A,B = 1 cycle/4 T; MVI A,data = 2/7; LDA addr = 4/13; CALL addr = 5/18; XTHL = 5/16).
Wait state: if READY is low at the end of T2, the processor inserts Twait states — used with slow memory.

8085 instruction set, stack and interrupts

Groups: data transfer (MOV, MVI, LXI, LDA, STA, LDAX, STAX, LHLD, SHLD, XCHG, IN, OUT — none affect flags), arithmetic (ADD, ADC, ADI, SUB, SBB, INR, DCR, INX, DCX, DAD, DAA), logical (ANA, ORA, XRA, CMP, CMA, RLC, RRC, RAL, RAR, STC, CMC), branch (JMP, conditional jumps, CALL/RET and conditionals, RST n, PCHL), machine control (PUSH, POP, XTHL, SPHL, EI, DI, SIM, RIM, HLT, NOP).
Note the traps: INR/DCR affect all flags except CY; INX/DCX and DAD affect no flag except DAD which affects only CY; CMP sets flags by A − operand but does not change A.
Stack: grows downward; PUSH decrements SP twice (high byte first at SP−1, low at SP−2), POP increments twice. Always initialise SP with LXI SP, before any CALL or PUSH.
Interrupts (5 pins, 8085): TRAP (RST 4.5 vector 0024H, non-maskable, edge+level triggered), RST 7.5 (003CH, edge-triggered, latched), RST 6.5 (0034H), RST 5.5 (002CH) — all level-triggered except 7.5 — and INTR (non-vectored; the device supplies the opcode, usually RST n or CALL, during the INTA̅ cycle).
Priority (highest → lowest): TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR. Software RST n vector = n × 8 (RST 0 = 0000H … RST 7 = 0038H).
SIM sets interrupt masks (M5.5, M6.5, M7.5 with MSE bit 3) and sends SOD; RIM reads masks, pending interrupts and SID.

8086 architecture: BIU, EU and pipelining

16-bit data bus, 20-bit address bus → 1 MB memory; 64 K I/O ports (16-bit port address). 40-pin DIP, +5 V, clock from 8284 clock generator (5 MHz 8086, 8 MHz 8086-2, 10 MHz 8086-1). Address/data lines AD0–AD15 and A16–A19 multiplexed with status S3–S6 are demultiplexed by 8282/74LS373 latches with ALE; 8286/74LS245 transceivers buffer data.
Bus Interface Unit (BIU): segment registers CS, DS, SS, ES; instruction pointer IP; adder for physical address; 6-byte instruction queue (prefetch).
Execution Unit (EU): ALU, flag register, control unit, general registers AX, BX, CX, DX (each splittable into AH/AL …), pointer/index registers SP, BP, SI, DI.
Pipelining: the BIU prefetches while the EU executes — the queue is refilled whenever ≥2 bytes are free; a jump/call flushes the queue. This overlap is the headline improvement over the 8085.
Flags (16-bit): CF, PF, AF, ZF, SF (conditional) + TF (trap/single-step), IF (interrupt enable), DF (direction for string ops), OF (overflow). Bits 1, 3, 5, 12–15 unused.
Memory organisation: two 512 KB banks — even (A0 = 0, data on D0–D7) and odd (selected by BHE̅, data on D8–D15). A word at an odd address needs two bus cycles; at an even address, one. Even-aligned data is therefore faster.
Registers with implicit roles: AX accumulator (MUL/DIV/string/IN-OUT), BX base (addressing), CX counter (LOOP, REP, shifts), DX port address and high word of MUL/DIV result, SI/DI string source/destination, BP stack-frame base.

8086 segmentation, addressing modes and modes of operation

Physical address = segment register × 10H + effective offset (segment base shifted left 4 bits). Segments are 64 KB, start on 16-byte paragraph boundaries, and may overlap.
Default segments: code → CS:IP; data → DS with BX/SI/DI/direct; stack → SS with SP/BP; string destination → ES:DI. Overridable with a segment-override prefix (e.g. MOV AL, ES:[BX]).
Advantages of segmentation: 1 MB addressed with 16-bit registers; programs are relocatable; code, data and stack separated. Limitation: a single segment cannot exceed 64 KB; far pointers need 32 bits.
Addressing modes (seven to eight, as examined): immediate (MOV AX,1234H), register (MOV AX,BX), direct (MOV AX,[2000H]), register indirect (MOV AX,[BX]), based (MOV AX,[BX+4]), indexed (MOV AX,[SI+4]), based-indexed (MOV AX,[BX+SI]), based-indexed with displacement (MOV AX,[BX+SI+6]); plus implied/string modes and relative addressing for jumps.
Minimum mode (MN/MX̄ = 1): the 8086 itself issues ALE, RD̄, WR̄, M/IO̅, DT/R̄, DEN̄, INTA̅ — a small single-processor system.
Maximum mode (MN/MX̄ = 0): status lines S̄0, S̄1, S̄2 are decoded by the 8288 bus controller, and the 8289 bus arbiter allows multiprocessing with an 8087 coprocessor or 8089 I/O processor; LOCK̄, QS0/QS1 (queue status) and RQ̄/GT̄0,1 replace HOLD/HLDA.
Bus cycle: 4 T-states (T1 address, T2 data direction setup, T3 data, T4 end); wait states inserted between T3 and T4 if READY is low.

8086 interrupts and instruction set highlights

256 interrupt types, vector table at 00000H–003FFH, 4 bytes per type (IP then CS). Type n vector address = n × 4.
Predefined: type 0 divide-by-zero, 1 single-step (TF), 2 NMI, 3 one-byte INT 3 breakpoint, 4 INTO overflow; types 5–31 reserved; 32–255 user/software (INT n). Hardware INTR is maskable by IF (CLI/STI); NMI is not.
Response sequence: push FLAGS, clear IF and TF, push CS, push IP, load new IP and CS from the vector table; IRET pops IP, CS, FLAGS.
Priority (as examined): divide-error/INT n/INTO > NMI > INTR > single-step.
Instruction groups: data transfer (MOV, XCHG, PUSH/POP, LEA, LDS/LES, IN/OUT, XLAT, LAHF/SAHF), arithmetic (ADD/ADC, SUB/SBB, INC/DEC, CMP, NEG, MUL/IMUL, DIV/IDIV, AAA/DAA/AAM/AAD), logical and bit (AND, OR, XOR, NOT, TEST, SHL/SHR/SAR, ROL/ROR/RCL/RCR), string (MOVSB/W, CMPS, SCAS, LODS, STOS with REP/REPE/REPNE and DF set by CLD/STD), control transfer (JMP, Jcc, LOOP/LOOPE/LOOPNE, CALL/RET near and far, INT/IRET), and processor control (CLC/STC/CMC, CLI/STI, HLT, WAIT, ESC, LOCK, NOP).
Peripheral chips examined with these CPUs: 8255 PPI (24 I/O lines, 3 ports, modes 0/1/2, BSR mode), 8259A PIC (8 levels, cascadable to 64), 8257/8237 DMA controller, 8253/8254 timer, 8251A USART, 8279 keyboard/display controller, 8155/8156 RAM-I/O-timer, 2764 EPROM and 6264 SRAM for memory interfacing. Memory-mapped I/O uses the full 16-bit/20-bit address with MEMR̄/MEMW̄ and all instructions; I/O-mapped (peripheral) I/O uses IN/OUT with IOR̄/IOW̄ and fewer address lines.

Key points

8085 - 8-bit data, 16-bit address, 64 KB memory, 256 I/O ports, 40 pins, 3 MHz typical, 5 interrupt pins.
8086 - 16-bit data, 20-bit address, 1 MB memory, 64 K I/O ports, 5–10 MHz, 256 interrupt types, pipelined.
Multiplexed bus - AD0–AD7 (8085) and AD0–AD15 (8086) carry address then data; ALE latches the address in T1.
T-state - one clock period; machine cycle = 3–6 T-states; instruction cycle = 1–5 machine cycles (8085).
Opcode fetch - 4 or 6 T-states, longer than the 3-T read/write cycles, identified by IO/M̄=0, S1=1, S0=1.
8085 flags - S, Z, AC, P, CY; parity flag is set for even parity; INR/DCR do not touch CY.
Stack - grows downward from SP; PUSH stores high byte first; SP must be initialised by LXI SP.
8085 interrupt priority - TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR; vectors 0024H, 003CH, 0034H, 002CH; RST n vector = 8n.
BIU vs EU - BIU fetches (6-byte queue, address generation, segments); EU decodes and executes — overlap gives pipelining.
Physical address - segment × 10H + offset; 20-bit result; segments of 64 KB on 16-byte boundaries.
BHE̅ and A0 - select odd and even memory banks; a word at an odd address costs two bus cycles.
Addressing modes (8086) - immediate, register, direct, register indirect, based, indexed, based-indexed, with displacement.
Min/Max mode - MN/MX̄ = 1: CPU generates control signals; = 0: 8288 decodes S̄0–S̄2 for multiprocessor systems.
8086 interrupt vector table - 1 KB at 00000H, 4 bytes/type (IP low, CS high); type n at 4n.
Segment defaults - CS:IP code, DS data, SS:SP/BP stack, ES:DI string destination; override prefix available.
Memory-mapped vs I/O-mapped I/O - full instruction set and address space vs only IN/OUT with a short port address.
Register pairs (8085) - BC, DE, HL; HL doubles as the memory pointer "M" and the only 16-bit add destination (DAD).
CX is the implicit counter - LOOP and REP-prefixed string instructions decrement CX; shifts/rotates take their count from CL.

Formulas and examples

Memory capacity = 2^{number of address lines} × (data bus width in bytes); 8085: 2¹⁶ × 1 B = 64 KB; 8086: 2²⁰ × 1 B = 1 MB
T-state duration T = 1 / f_internal; for the 8085, f_internal = f_crystal / 2
Execution time of an instruction = (number of T-states) × T
Physical Address (8086) PA = (Segment register value × 10H) + Effective Offset — 20-bit result, hexadecimal
Effective Address EA = base (BX or BP) + index (SI or DI) + displacement
Software RST vector (8085) = n × 8 (decimal) ; 8086 interrupt vector address = type × 4
Number of chips required = (total memory required) / (capacity of one chip); address lines to the chip = log₂(chip locations), rest go to the decoder

Example 1 — 8085 T-state and delay loop. A 8085 system uses a 6.144 MHz crystal.

Internal clock f = 6.144/2 = 3.072 MHz → T = 1/3.072 MHz = 325.52 ns.
A delay loop LOOP: DCR C (4 T) ; JNZ LOOP (10 T when taken) = 14 T per pass = 14 × 325.52 ns = 4.557 µs.
For C = 100: delay ≈ 100 × 4.557 µs = 455.7 µs, minus 3 T on the last (not-taken) JNZ: 455.7 − 0.98 ≈ 454.7 µs.
To get about 1 ms, two nested loops or a larger count in a 16-bit (DCX-based) loop are needed.

Example 2 — 8086 physical address. CS = 1A2BH, IP = 03C4H.

PA = 1A2B0H + 03C4H = 1A674H.
Code segment range = 1A2B0H to 1A2B0H + FFFFH = 1A2B0H–2A2AFH.
If DS = 2000H and the instruction is MOV AX,[BX+SI+0010H] with BX = 0100H, SI = 0020H: EA = 0100 + 0020 + 0010 = 0130H, PA = 20000H + 0130H = 20130H.

Example 3 — 8085 instruction timing. Count machine cycles and T-states for the sequence MVI A, 32H; LXI H, 2050H; MOV B, M; STA 2060H; HLT.

Instruction	Machine cycles	T-states
MVI A, 32H	2 (OF + MR)	7
LXI H, 2050H	3 (OF + MR + MR)	10
MOV B, M	2 (OF + MR)	7
STA 2060H	4 (OF + MR + MR + MW)	13
HLT	2	5
Total	13	42

At 3.072 MHz (T = 325.52 ns), total time = 42 × 325.52 ns ≈ 13.67 µs.

Example 4 — memory interfacing and address decoding. Build 16 KB of RAM for an 8085 using 4 K × 8 chips, starting at 4000H.

Chips needed = 16 K / 4 K = 4 chips.
Each chip has 4 K = 2¹² locations → A0–A11 go to the chip; A12, A13 select the chip via a 2-to-4 decoder; A14, A15 enable the decoder.
Address ranges: chip 0 = 4000H–4FFFH, chip 1 = 5000H–5FFFH, chip 2 = 6000H–6FFFH, chip 3 = 7000H–7FFFH (A15 A14 = 01 enables the decoder throughout).

Example 5 — 8085 program, sum of a block. Add ten 8-bit numbers from 2050H, storing the 16-bit sum at 2070H–2071H.

      LXI H, 2050H   ; pointer to data
      MVI C, 0AH     ; count = 10
      LXI D, 0000H   ; DE = running sum
NEXT: MOV A, M
      ADD E
      MOV E, A
      JNC SKIP
      INR D          ; propagate carry
SKIP: INX H
      DCR C
      JNZ NEXT
      XCHG           ; HL <- sum
      SHLD 2070H     ; store low byte at 2070H, high at 2071H
      HLT

If the ten bytes are each 40H (64 decimal), sum = 640 decimal = 0280H → 2070H holds 80H, 2071H holds 02H.

8085 vs 8086 comparison

	8085	8086
Data / address bus	8-bit / 16-bit	16-bit / 20-bit
Memory, I/O space	64 KB, 256 ports	1 MB, 64 K ports
Architecture	Single unit, fetch then execute	BIU + EU, pipelined (6-byte queue)
Clock	3 MHz (crystal ÷ 2, on-chip)	5–10 MHz, external 8284
Registers	A, B, C, D, E, H, L, SP, PC	AX–DX, SP, BP, SI, DI, IP, CS/DS/SS/ES
Flags	5	9
Interrupts	5 pins, fixed vectors	256 types, vector table at 00000H
Multiply / divide	Not available (routine needed)	MUL, IMUL, DIV, IDIV in hardware
Modes	One	Minimum and maximum
Transistors	~6,500	~29,000

Where it is used

University labs and skill tests: 8085/8086 trainer kits (Vinytics, Scientech, Dynalog) with 8255/8253/8279 interfacing experiments; part of AICTE model curriculum microprocessor labs and polytechnic practicals.
Entry-level embedded interviews: Bosch, Continental, Tata Elxsi, KPIT, L&T Technology Services, Cyient, Wipro and Qualcomm screening rounds ask bus cycles, interrupt latency, memory maps and addressing modes before moving to ARM or 8051.
PSU and defence recruitment: ISRO, DRDO, BEL, HAL, BHEL, NTPC, railways (RRB JE) and GATE EC/EE/CS/IN papers examine physical-address computation, timing diagrams and instruction counts.
Legacy industrial systems: 8085- and 8086-class CPUs still appear in older process controllers, weighing machines, CNC retrofits, lift controllers and railway signalling panels maintained in India, where repair and reverse-engineering need this knowledge.
x86 lineage: 8086 real mode, segmentation and the interrupt vector table remain the boot path of every x86 PC and the basis for BIOS/bootloader, firmware and OS-internals work.
VLSI and design verification: 8085/8086-style cores are standard verification and FPGA/HDL projects (writing a soft CPU, datapath and control-unit design) in VLSI job portfolios.

Interview questions

Q: Why is the 8085 address/data bus multiplexed and how is it demultiplexed? A: To keep the chip at 40 pins; AD0–AD7 carry the low address in T1 and data in T2–T3, and an external latch (74LS373) clocked by ALE holds the low address for the rest of the cycle.
Q: What is the difference between a machine cycle and an instruction cycle? A: A machine cycle is one bus transaction (3–6 T-states, e.g. an opcode fetch or memory read); an instruction cycle is all the machine cycles needed to complete one instruction.
Q: How is the 20-bit physical address formed in the 8086? A: The segment register is shifted left by four bits (multiplied by 10H) and added to the 16-bit effective offset in the BIU's dedicated adder.
Q: What advantage does the 8086's instruction queue give? A: The BIU prefetches up to six bytes while the EU executes, so fetch and execute overlap; the gain is lost on a branch because the queue is flushed.
Q: Which 8085 interrupt is non-maskable, and which is edge-triggered? A: TRAP is non-maskable (vector 0024H) and responds to a rising edge held high; RST 7.5 is the edge-triggered, latched one among the RST interrupts.
Q: Difference between memory-mapped and I/O-mapped I/O? A: Memory-mapped I/O treats the device as a memory location — full address space and all instructions usable, but memory space is consumed; I/O-mapped uses IN/OUT with an 8-bit (8085) port address and the IO/M̄ line, keeping memory free.
Q: Why is accessing a word at an odd address slower in the 8086? A: The word straddles both memory banks, so the processor needs two bus cycles (with BHE̅/A0 combinations) instead of one.
Q: What is the difference between minimum and maximum mode? A: In minimum mode (MN/MX̄ = 1) the 8086 generates the control signals itself; in maximum mode it issues status S̄0–S̄2 which the 8288 bus controller decodes, enabling coprocessors and multiprocessing.
Q: What happens on the stack when the 8086 services an interrupt? A: FLAGS, then CS, then IP are pushed, IF and TF are cleared, and the new CS:IP is loaded from the 4-byte vector at type × 4; IRET restores IP, CS and FLAGS in reverse.
Q: CALL versus PUSH — what is the difference? A: CALL pushes the return address automatically and transfers control; PUSH only saves a register pair and does not change the program flow.
Q: Why does the 8085 need no DMA controller logic of its own? A: The HOLD/HLDA handshake lets an external 8257/8237 take over the buses — the 8085 tri-states its buses and acknowledges with HLDA.
Q: How many T-states does a minimum 8086 bus cycle take and where do wait states go? A: Four (T1–T4), with Tw inserted between T3 and T4 whenever READY is sampled low — used for slow memory or peripherals.
Q: Which flags does the 8085 INR instruction affect? A: S, Z, AC and P — but not CY, which is why INR cannot be used for multi-byte counting.

Common mistakes

Forgetting that the 8085 crystal frequency is twice the internal clock, so every T-state and delay calculation comes out double.
Writing the physical address as segment + offset without shifting the segment left by four bits (× 10H).
Assuming segments must be separate — they may overlap, and a 64 KB limit per segment still applies.
Treating INR/DCR as if they set the carry flag, or expecting INX/DCX to affect any flag.
Using CALL or PUSH before initialising SP with LXI SP, which corrupts data at the default stack location.
Mixing up PUSH/POP byte order (high byte goes to the higher address, SP−1) and forgetting that POP order must mirror PUSH order.
Assigning three T-states to an opcode fetch (it is four, or six for instructions like CALL and PUSH) and ignoring extra cycles in multi-byte instructions.
Confusing RST 5.5/6.5/7.5 hardware vectors with software RST n (8n) addresses, or writing the 8086 vector as type × 2 instead of type × 4.
Decoding memory without accounting for the unused higher address lines, which creates unintended foldback (multiple addresses selecting the same chip).