PCB design, EMI and EMC

In short

A printed circuit board (PCB) is the mechanical and electrical substrate that holds an embedded system together, and above a few megahertz its copper stops behaving like ideal wire and starts behaving like inductors, capacitors and antennas. Electromagnetic interference (EMI) is the unwanted energy a board emits or picks up; electromagnetic compatibility (EMC) is the design discipline that makes a product neither disturb others nor be disturbed itself. Every electronic product sold in India needs EMC evidence — through BIS compulsory registration, TEC's MTCTE scheme for telecom equipment and the applicable IS/CISPR standards — so hardware teams at Bosch, Continental, Tata Elxsi, L&T Technology Services, HAL, BEL, ISRO and medical/automotive suppliers interview heavily on it. In exams it appears as layer stack-up, grounding, decoupling, transmission-line and shielding questions in Microprocessors/Embedded System Design and Electronic Product Design papers; in GATE and PSU papers it surfaces through transmission-line reflection, skin depth and impedance calculations.

Explained

PCB fundamentals and fabrication

• Substrate: FR-4 glass-epoxy is standard, relative permittivity εr ≈ 4.2–4.5 at 1 GHz (falls with frequency), loss tangent tan δ ≈ 0.02. High-speed/RF boards use Rogers RO4350B (εr ≈ 3.48, tan δ ≈ 0.0037) or polyimide for high temperature.
• Copper weight: 1 oz/ft² = 35 µm thickness (1 oz is the default); 2 oz = 70 µm for power boards. Thickness decides current capacity and etch resolution.
• Standard board thickness: 1.6 mm; 0.8 mm and 1.0 mm common for compact IoT modules.
• Layer counts: 1-layer (consumer, LED lamps), 2-layer (hobby, simple MCU boards), 4-layer (most professional MCU boards), 6–12+ layers (SoC, DDR, BGA fan-out).
• Process flow: schematic → netlist → footprint/library → placement → stack-up → routing → DRC → copper pour → Gerber/ODB++ + drill + pick-and-place files → fabrication (lamination, drilling, plating, etch, solder mask, silkscreen, surface finish) → assembly (solder paste, SMT placement, reflow) → test.
• Surface finishes: HASL (cheap, uneven), ENIG (flat, good for BGA/fine pitch, costlier), OSP (cheap, short shelf life), immersion silver/tin.
• Via types: through-hole, blind (outer to inner), buried (inner to inner), micro-via (laser, HDI). Via-in-pad needs filling and plating over.
• Design rules (typical Indian fab, e.g. 2-layer/4-layer service): 6 mil (0.15 mm) trace/space and 0.3 mm drill are routine economy limits; 3–4 mil is HDI and costs more.
• DFM/DFT: keep test points, fiducials for pick-and-place, thermal reliefs on through-hole pads in planes, courtyard clearance, panelisation with mouse-bites or V-score.

Layer stack-up, grounding and return current

• The return current is the whole story. At DC, return current takes the path of least resistance; above roughly 1–10 kHz it takes the path of least inductance, which is directly beneath the signal trace on the nearest plane.
• Never split a ground plane under a signal trace. A slot or split forces the return current to detour around it, creating a large loop that both radiates and picks up noise. This is the single most examined EMC rule.
• Recommended 4-layer stack-up: Signal / GND / PWR / Signal. The solid ground on layer 2 gives every top-layer trace a tight return path; GND and PWR adjacent form interplane capacitance.
• A poorer but common alternative is Signal / PWR / GND / Signal — the top layer then references power, which is noisier.
• Image plane: an unbroken plane adjacent to signals reduces radiation by 10–20 dB over a 2-layer board with ground traces.
• Grounding schemes: *single-point (star)* ground for low-frequency analogue and audio; *multi-point* ground (many vias to a plane) above about 1 MHz, since ground wires become inductive; *hybrid* ground uses capacitors to make a single-point DC ground look multi-point at RF.
• Analogue/digital ground: modern practice for mixed-signal ADC/DAC boards is one solid ground plane with partitioned placement (analogue parts over the analogue region, digital over the digital region) rather than split planes joined by a bridge — the split is a classic source of EMI failures.
• Ground bounce / simultaneous switching noise (SSN): when many outputs switch, di/dt through the package and plane inductance lifts the chip's local ground: V = L·di/dt. Fixed by more ground pins/vias, lower-inductance decoupling and slower edges.
• Via stitching: placing ground vias every λ/20 (and around board edges) ties planes together and suppresses edge radiation; 20-H rule — pull the power plane back from the board edge by 20× the dielectric spacing to contain fringing fields (useful rule of thumb, not an absolute law).

Power distribution network (PDN) and decoupling

• The PDN must present low impedance from DC to the highest harmonic of the switching current: Ztarget = ΔVallowed / ΔImax.
• Bulk capacitors (10–100 µF tantalum/electrolytic, near the regulator) handle low-frequency and load-step demand.
• Decoupling/bypass capacitors (100 nF ceramic X7R, one per IC power pin) supply high-frequency switching charge locally so the current loop stays tiny.
• A real capacitor is C in series with ESR and ESL — it resonates at SRF = 1/(2π√(L·C)) and is *inductive above it*. A 100 nF 0402 with ~0.6 nH loop inductance self-resonates near 20 MHz, so it does nothing useful at 300 MHz.
• Placement beats value. Put the capacitor within a few millimetres of the pin, use short fat traces, and give each pad its own via to the plane; via and trace inductance (~0.5–1 nH each) dominate.
• Paralleling many identical caps lowers ESL and raises the usable frequency; mixing very different values (e.g. 10 µF with 1 nF) can create anti-resonance peaks between their SRFs.
• Interplane capacitance of an adjacent GND/PWR pair is nearly ideal (very low ESL) and is the best decoupling above a few hundred MHz: C = ε0εr·A/d.
• Ferrite bead in a supply branch (e.g. AVDD for an ADC) is a resistor at RF; it must be sized by its impedance at the noise frequency and its DC resistance/saturation current, and can resonate with the following capacitor if undamped.

Signal integrity: transmission lines, reflections and crosstalk

• A trace must be treated as a transmission line when its one-way propagation delay exceeds about 1/6 (conservatively 1/10) of the signal's rise time — i.e. tr < 6 × tpd × length.
• Propagation delay on FR-4: microstrip ≈ 1.7 ns/ft ≈ 5.6 ps/mm (εeff ≈ 2.9–3.2); stripline ≈ 2.1 ns/ft ≈ 7.0 ps/mm (fully embedded in εr ≈ 4.3).
• Common target impedances: 50 Ω single-ended (RF, most digital), 90 Ω differential (USB 2.0), 100 Ω differential (Ethernet, LVDS, HDMI), 85 Ω or 90 Ω (PCIe/SATA variants).
• Reflections occur at any impedance discontinuity; the reflection coefficient Γ = (ZL − Z0)/(ZL + Z0). Symptoms: overshoot, undershoot, ringing, false clocking, EMI from fast ringing.
• Termination types: *series (source)* — resistor at the driver so Rs + Rout = Z0, best for point-to-point CMOS and uses no DC power; *parallel* — R = Z0 to ground at the receiver (burns DC current); *Thevenin* — two resistors to VCC and GND; *AC/RC* — resistor plus capacitor, no DC path; *diode* clamps for overshoot.
• Crosstalk: capacitive and inductive coupling between adjacent traces. *NEXT* (near-end, backward) and *FEXT* (far-end, forward). Reduce by the 3-W rule (centre-to-centre spacing ≥ 3× trace width), by keeping traces close to their reference plane (halving height quarters coupling), and by avoiding long parallel runs; guard traces help only if stitched to ground with dense vias.
• Length matching: match differential pairs intra-pair (skew typically < 5 mil / 0.13 mm) and match buses (DDR byte lanes) to the clock using serpentine routing; keep differential pairs tightly and uniformly coupled.
• Clock routing: shortest possible, one layer, no stubs, reference to solid ground, guard with ground vias; never route a clock across a plane split or near the board edge or a connector.
• Skin effect: current crowds into a surface layer of depth δ = √(ρ/(π f µ)) — about 2.1 µm in copper at 1 GHz — so AC resistance and conductor loss rise as √f; dielectric loss rises roughly linearly with f.

EMI: sources, coupling, and emission/immunity requirements

• EMI model = source → coupling path → victim. Any of the three can be attacked; the coupling path is usually the cheapest.
• Sources: clocks and their harmonics, switching regulators (SMPS, 100 kHz–2 MHz plus harmonics), motor drives and PWM, relays and contactors, ESD events, lightning surge, RF transmitters.
• Coupling mechanisms: (1) conducted through power/signal wires, (2) capacitive (electric field) coupling, (3) inductive (magnetic field) coupling, (4) radiated (far-field) coupling.
• Differential-mode emission comes from the signal current loop — proportional to loop area, current and f²; fixed by shrinking loops. Common-mode emission comes from stray ground voltage driving cables as antennas — proportional to cable length, CM current and f; usually the dominant failure mode and fixed by filtering/chokes and better grounding.
• Near field vs far field: boundary at r = λ/2π. Within the near field, a high-impedance (electric) field or low-impedance (magnetic) field dominates; beyond it the wave impedance settles at 377 Ω.
• Antenna effects: a trace or slot becomes an efficient radiator near λ/4 or λ/2; a 1 GHz harmonic has λ = 300 mm, so λ/4 = 75 mm — an unstitched slot or a dangling cable of that size radiates well.
• Emission tests: *conducted emission* typically 150 kHz–30 MHz measured with a LISN (line impedance stabilisation network); *radiated emission* typically 30 MHz–1 GHz (up to 6 GHz for equipment with internal frequencies above 108 MHz) in an anechoic/OATS chamber, with quasi-peak and average detectors.
• Immunity tests (IEC 61000-4 series): -2 ESD (contact ±4 kV, air ±8 kV typical), -3 radiated RF immunity (3 or 10 V/m), -4 electrical fast transient/burst, -5 surge, -6 conducted RF immunity, -8 power-frequency magnetic field, -11 voltage dips and interruptions.
• Class A vs Class B: Class A is for industrial/commercial environments; Class B is for domestic environments and has limits about 10 dB stricter.

EMC design techniques and standards in India

• Shrink the loop: minimise the area enclosed by signal-and-return and by supply-and-return. Loop area is the first-order lever on radiation.
• Slow the edges: use series resistors or slew-rate-controlled drivers; a 1 ns edge has significant energy to about 0.35/1 ns = 350 MHz, a 5 ns edge only to 70 MHz.
• Spread-spectrum clocking (SSC): dithers the clock by about ±0.5–2% to spread harmonic energy and reduce measured peaks by 6–15 dB (it reduces the *measurement*, not total energy, and can break synchronous links if misused).
• Filtering: pi filters and feed-through capacitors at connectors; common-mode chokes on USB/Ethernet/CAN/power pairs; X capacitors (line-to-line) and Y capacitors (line-to-earth, leakage-current limited) in mains input filters.
• Shielding: a conductive enclosure or can; shielding effectiveness SE(dB) = A (absorption) + R (reflection) + B (multiple-reflection correction). Apertures dominate: a slot longer than λ/20 leaks badly; many small holes beat one large slot. Gaskets and 360° cable-shield terminations are essential.
• Cable treatment: cables are the main antennas. Terminate shields 360° to the chassis at the connector (not with a long "pigtail"), filter every wire entering/leaving the enclosure at the point of entry.
• ESD protection: TVS diodes placed right at the connector, ahead of any trace that goes to a chip; low parasitic capacitance (< 1 pF) for USB/HDMI; a ground return path for the ESD current that does not pass under sensitive circuits; keep spark gaps / creepage at the connector.
• Indian regulatory framework (verify the current scope before certifying — lists and dates are revised often):
  • BIS under the *BIS Act, 2016* runs the Compulsory Registration Scheme (CRS) for notified electronics (IT equipment, LED products, power adapters, batteries, etc.) under the MeitY *Electronics and IT Goods (Requirements for Compulsory Registration) Order*. CRS is primarily safety (IS 13252 series, adopting IEC 60950/62368), with EMC requirements applying to several product categories.
  • TEC (Telecommunication Engineering Centre, DoT) runs MTCTE — Mandatory Testing and Certification of Telecom Equipment — under the Indian Telegraph (Amendment) Rules, with EMC as one of the Essential Requirements; now operating under the *Telecommunications Act, 2023* framework.
  • WPC (Wireless Planning & Coordination wing, DoT) grants ETA/licences for radio equipment and governs the de-licensed 2.4 GHz / 5 GHz bands.
  • AERB / CDSCO (medical devices, IEC 60601-1-2 EMC), AIS-004 (Part 3) / AIS-137 for automotive EMC under CMVR, tested at ARAI, ICAT and NATRAX.
  • Indian EMC standards are IS adoptions of CISPR/IEC: IS 6873 (CISPR-based emission/immunity for several product families), CISPR 11 (ISM equipment), CISPR 32 / CISPR 14-1 (multimedia and household appliances), CISPR 25 (automotive components), IS 14700 series (= IEC 61000 series).
  • Indian EMC test labs include ERTL (North/East/West/South, under STQC, MeitY), SAMEER, CPRI Bengaluru, ARAI Pune and several NABL-accredited private labs; a full radiated + conducted + immunity campaign typically costs in the range of ₹2–8 lakh and days to weeks of chamber time, which is why pre-compliance scanning on the bench is standard practice.

Key points

• Return current - above a few kHz it flows directly under the trace on the nearest plane; design the return path, not just the trace.
• Never split a plane under a trace - the detoured return current makes a large loop that radiates and picks up noise.
• Loop area - radiated emission from differential-mode current is proportional to loop area × current × f²; shrink loops first.
• Common-mode emission - caused by stray ground potential driving cables; usually the real cause of radiated test failures.
• Decoupling capacitor - 100 nF per power pin placed within millimetres; its mounting inductance, not its capacitance, sets the high-frequency limit.
• Self-resonant frequency SRF = 1/(2π√(LC)); above SRF a capacitor is inductive and stops decoupling.
• Transmission line criterion - treat as a line when rise time < ~6 × propagation delay of the trace.
• Z₀ targets - 50 Ω single-ended, 90 Ω differential USB, 100 Ω differential Ethernet/LVDS.
• Reflection coefficient Γ = (Z_L − Z₀)/(Z_L + Z₀); series termination at the source is the standard CMOS fix.
• 3-W rule - keep trace centre-to-centre spacing at least 3× the trace width to cut crosstalk to roughly 1%.
• Ground bounce V = L·di/dt - caused by simultaneous switching; cured by more ground vias and slower edges.
• Bandwidth of a digital edge BW ≈ 0.35/t_r; slower edges contain less high-frequency energy.
• Skin depth δ = √(ρ/πfµ) ≈ 2.1 µm in copper at 1 GHz; AC resistance rises as √f.
• 20-H rule and via stitching - pull back power planes from the edge and stitch ground vias every λ/20 to stop edge radiation.
• Shielding effectiveness SE = A + R + B; apertures larger than λ/20 destroy a good shield.
• LISN - stabilises the mains impedance so conducted emission (150 kHz–30 MHz) can be measured repeatably.
• Class A vs Class B - industrial vs domestic limits; Class B is about 10 dB tighter.
• Indian compliance - BIS CRS (BIS Act, 2016), TEC MTCTE for telecom, WPC ETA for radio, AIS/CISPR 25 for automotive, tested at ERTL/SAMEER/ARAI.

Formulas and examples

Example 1 — Does this trace need termination? A 74LVC buffer with a 1 ns rise time drives a trace on the top layer of an FR-4 board (microstrip, t_pd ≈ 5.6 ps/mm). Trace length = 80 mm.

• Critical length l_crit = t_r/(6·t_pd) = 1000 ps / (6 × 5.6 ps/mm) = 1000/33.6 ≈ 29.8 mm.
• 80 mm > 29.8 mm, so the trace must be treated as a transmission line and terminated.
• Knee frequency f_knee = 0.35/1 ns = 350 MHz — so the board must behave well to at least 350 MHz.
• If the driver output impedance is 20 Ω on a 50 Ω line, add a series resistor of 50 − 20 = 30 Ω (33 Ω standard value) at the driver pin.

Example 2 — Reflection from an unterminated input. A 50 Ω trace ends at a CMOS input of effectively 10 kΩ. A 3.3 V step travels down the line.

• Γ = (10 000 − 50)/(10 000 + 50) = 9950/10050 = +0.990.
• Reflected step = 0.990 × 3.3 = 3.27 V; voltage at the receiver = 3.3 + 3.27 = 6.57 V momentarily.
• That is roughly double the rail and will trigger the input clamp diodes — the classic cause of overshoot damage and ringing. With a 33 Ω series resistor at the source, the return reflection is absorbed on arrival and the receiver settles cleanly.

Example 3 — Decoupling capacitor: is it still a capacitor at 200 MHz? A 100 nF 0603 capacitor with ESL = 1.2 nH is mounted with two vias and short traces adding ≈ 1.3 nH, so L_total = 2.5 nH.

• f_SRF = 1/(2π√(2.5 × 10⁻⁹ × 100 × 10⁻⁹)) = 1/(2π√(2.5 × 10⁻¹⁶)) = 1/(2π × 1.581 × 10⁻⁸) ≈ 10.1 MHz.
• At 200 MHz the branch is inductive: |Z| ≈ 2πfL = 2π × 2 × 10⁸ × 2.5 × 10⁻⁹ ≈ 3.14 Ω — far too high for a PDN target of, say, 0.1 Ω.
• Fix: cut mounting inductance (via-in-pad, 0402 package → L_total ≈ 1 nH, SRF ≈ 15.9 MHz, |Z| at 200 MHz ≈ 1.26 Ω), parallel several capacitors, and rely on interplane capacitance plus on-die capacitance above ~100 MHz.

Example 4 — Loop area and radiated emission. A 50 MHz clock drives 20 mA over a trace whose signal-and-return loop encloses 4 cm². Measured at 3 m, take the third harmonic (150 MHz).

• E ≈ 263 × 10⁻¹⁴ × (f² · A · I)/r = 263 × 10⁻¹⁴ × ((1.5 × 10⁸)² × 4 × 0.02)/3.
• (1.5 × 10⁸)² = 2.25 × 10¹⁶; × 4 = 9 × 10¹⁶; × 0.02 = 1.8 × 10¹⁵; ÷ 3 = 6.0 × 10¹⁴.
• E ≈ 263 × 10⁻¹⁴ × 6.0 × 10¹⁴ = 1578 µV/m ≈ 64.0 dBµV/m.
• Now route the clock over a solid ground plane 0.2 mm below, so the loop is 0.2 mm × 100 mm = 0.2 cm² — 20× smaller. E falls to 78.9 µV/m ≈ 37.9 dBµV/m, a 26 dB improvement from layer stack-up alone. (CISPR 32 Class B radiated limit at 3 m is of the order of 40 dBµV/m in the 30–230 MHz band, quasi-peak — so the loose loop fails and the plane-referenced version just passes; confirm the exact limit and distance in the current edition.)

Example 5 — Trace width for 2 A on an outer layer. Requirement: 2 A, ΔT = 10 °C rise, 1 oz copper (1.4 mil thick), external trace (k = 0.048).

• Rearranged: A = (I/(k·ΔT^0.44))^1/0.725. ΔT^0.44 = 10^0.44 = 2.754; k·ΔT^0.44 = 0.048 × 2.754 = 0.1322.
• I/0.1322 = 2/0.1322 = 15.13; A = 15.13^1/0.725 = 15.13^1.379 ≈ 42.6 mil².
• Width = 42.6/1.4 ≈ 30 mil ≈ 0.77 mm. For the same current on an *internal* layer (k = 0.024), A ≈ 112 mil² → width ≈ 80 mil ≈ 2.0 mm. Internal traces need roughly 2.5× the width because they cannot convect heat away.

Where it is used

• Automotive electronics: ECUs, instrument clusters, BMS and EV traction inverters at Bosch, Continental, Visteon, Tata Elxsi, KPIT and L&T Technology Services — tested to CISPR 25 and AIS-004 (Part 3) at ARAI Pune, ICAT Manesar and NATRAX.
• Telecom and consumer hardware: routers, set-top boxes, smart meters and chargers needing BIS CRS registration and TEC MTCTE approval; EMC pre-compliance at ERTL and SAMEER labs.
• Defence, space and avionics: BEL, HAL, DRDO labs, ISRO/VSSC and L&T Defence design to MIL-STD-461 and DO-160 — shielded enclosures, filtered connectors, 360° backshells.
• Medical devices: patient monitors, ECG and infusion pumps from Indian manufacturers must meet IEC 60601-1-2 EMC under CDSCO's Medical Devices Rules, 2017.
• Industrial and power electronics: VFDs, UPS and solar inverters (Kirloskar, Delta, CPRI-tested) where SMPS and IGBT switching make conducted emission the hard problem.
• Job roles: hardware design engineer, PCB layout engineer (Altium Designer, Cadence Allegro, Mentor Xpedition, KiCad), signal-integrity engineer (HyperLynx, ADS, HFSS), EMC/compliance engineer, product validation engineer.

Interview questions

• Q: Why must you never route a high-speed signal over a split in the ground plane? A: The return current cannot follow the trace and must detour around the split, creating a large current loop that radiates strongly and makes the board susceptible to pick-up; it also changes the trace impedance locally.
• Q: What decides where return current flows on a PCB? A: At DC it takes the path of lowest resistance, but above roughly 1–10 kHz it takes the path of lowest inductance, which is the copper directly beneath the trace on the nearest reference plane.
• Q: Why is the placement of a decoupling capacitor more important than its value? A: The loop inductance of the mounting (pads, traces, vias) is in series with the capacitor and dominates its impedance at high frequency; a perfectly chosen capacitor placed 20 mm away is useless.
• Q: What is the self-resonant frequency of a capacitor and why does it matter? A: f = 1/(2π√(LC)) where L is the total series inductance; above this frequency the component is inductive and no longer decouples, so you need smaller packages, parallel caps or plane capacitance.
• Q: When should a PCB trace be treated as a transmission line? A: When the signal rise time is shorter than about six times the one-way propagation delay of the trace — roughly 30 mm on FR-4 microstrip for a 1 ns edge.
• Q: Difference between differential-mode and common-mode emission? A: Differential-mode emission comes from the intended signal current loop and scales with loop area and f²; common-mode emission comes from a stray ground voltage driving attached cables as antennas, scales with cable length and f, and usually dominates real test failures.
• Q: How would you fix a board that fails radiated emission at 250 MHz? A: Find the source with a near-field probe and spectrum analyser, check whether it moves with cables attached (common-mode) or not, then shrink the offending loop, add a common-mode choke or filter at the connector, slow the edge, or add ground stitching — and re-scan after each change.
• Q: Why is series termination preferred for CMOS point-to-point links? A: It matches the source to the line with one resistor, absorbs the returning reflection, draws no DC current and preserves full logic swing at the receiver after one round trip.
• Q: What is the 3-W rule? A: Keeping trace centre-to-centre spacing at least three times the trace width reduces crosstalk to roughly 1% of the aggressor signal; bringing traces closer to their reference plane helps even more.
• Q: Should analogue and digital grounds be split on a mixed-signal board? A: Generally no — current practice is a single solid ground plane with analogue and digital parts physically partitioned over their own regions, because a split plane forces return-current detours; split grounds are only justified in specific isolated or very-low-level analogue designs.
• Q: What does a LISN do? A: It presents a defined, stabilised RF impedance to the equipment under test and couples the conducted noise on the mains to the measuring receiver, making conducted-emission results repeatable across labs.
• Q: Which Indian approvals would a Wi-Fi smart plug need? A: BIS registration under the CRS where the product category is notified, WPC/ETA for the 2.4 GHz radio, and EMC/safety testing to the applicable IS/CISPR standards at an accredited lab — the exact scope should be checked against the current MeitY and WPC notifications.
• Q: What is the 20-H rule? A: Recessing the power plane from the board edge by 20 times the dielectric separation from the ground plane confines fringing fields between the planes and reduces edge radiation; it is a useful heuristic rather than a guaranteed law.

Common mistakes

• Treating ground as an equipotential "zero volts" node — every via, trace and plane slot has inductance, and V = L·di/dt makes ground move.
• Splitting ground planes or routing across a moat under the belief it isolates noise; it almost always worsens EMI.
• Choosing decoupling capacitor values from a table while ignoring mounting inductance, package size and self-resonance.
• Leaving EMC to the end — adding shields and filters after layout costs far more than a correct stack-up at the start, and chamber retests are billed each time.
• Confusing the clock frequency with the frequency content of the signal: a 10 MHz clock with a 1 ns edge radiates up to 350 MHz.
• Forgetting to apply the right IPC-2221 constant (k = 0.024 internal, 0.048 external) or using mm instead of mil in trace-width calculations.
• Running a differential pair with uneven lengths, uncoupled sections or a reference-plane change at a via, then wondering why common-mode noise appears.

Related topics

Embedded interfaces: UART, SPI and I2C · Microcontroller peripherals: timers, ADC, PWM and interrupts · Transmission lines and waveguides · Antennas and radiation · Power electronics and SMPS design · Electronic measurements and instrumentation