Multistage and differential amplifiers

In short

A multistage amplifier cascades two or more amplifying stages so that the overall gain is the product of the stage gains, while each stage is chosen for what it does best — high input resistance, high gain, or low output resistance. A differential amplifier (emitter- or source-coupled pair) amplifies the difference between two inputs and rejects whatever is common to both, which is why it is the input stage of every op-amp, comparator, ADC front end and instrumentation amplifier. The two topics sit together because the classic analog IC is a differential pair followed by a gain stage and a buffer. This is heavy GATE EC territory (half-circuit analysis, CMRR, cascode gain, bandwidth shrinkage) and is asked in ISRO, DRDO, BEL, BARC and PSU interviews, and in analog design screening at Texas Instruments India, Analog Devices, Qualcomm, Intel, Cadence and Synopsys.

Explained

Why cascade, and what cascading costs

• Overall voltage gain Av = Av1 × Av2 × … × Avn, where each stage gain must be computed with the next stage's input resistance as its load — this loading is the single most common exam trap.
• In decibels the gains add: Av(dB) = 20 log₁₀|Av| for voltage/current ratios, 10 log₁₀ for power ratios. A 6 dB loss in an interstage network simply subtracts.
• Input resistance of the cascade = Rin of stage 1; output resistance = Rout of the last stage. So stage order matters: a CC (emitter follower) or CD stage first for high Rin, CE/CS in the middle for gain, CC/CD last for low Rout.
• Cost of cascading: bandwidth shrinks, phase shift accumulates (a risk when feedback is applied), noise of the first stage dominates, DC drift accumulates in direct-coupled chains, and cost/power rise.
• Noise rule: total input-referred noise is dominated by stage 1 (Friis), so the first stage is designed for low noise and the later stages for gain.

Coupling between stages

• RC (capacitive) coupling: coupling capacitor blocks DC so each stage is biased independently; cheap, compact, good mid-band response, but no DC/low-frequency response and poor impedance matching. Standard for audio pre-amplifiers.
• Transformer coupling: gives impedance matching (turns ratio n = √(RL′/RL)) and maximum power transfer with no DC drop across the primary; bulky, costly, poor frequency response (leakage inductance and winding capacitance), used in output/power and RF tuned stages.
• Direct (DC) coupling: no capacitors, amplifies from DC upwards, essential inside ICs where large capacitors cannot be made; but the DC level shifts stage to stage (needing level shifters — a pnp stage, a diode/resistor string or a current source) and thermal drift is amplified by all following stages. This drift problem is the historical reason the differential pair was invented.
• Optical/tuned coupling: optocouplers for isolation, LC tank coupling in IF/RF strips.

Frequency response of a cascade

• Mid-band gain multiplies; the overall upper cut-off falls and the lower cut-off rises, so bandwidth always shrinks.
• For n identical non-interacting stages: set the product magnitude 3 dB down → (1 + (f/f_H)²)^n/2 = √2 → f_H* = f_H √(2^1/n − 1) and f_L* = f_L / √(2^1/n − 1).
• Rise-time rule: t_r ≈ 0.35/f_H for a single-pole stage; for a cascade t_r(total) ≈ 1.1 √(t_r1² + t_r2² + …).
• Gain–bandwidth trade: raising n raises gain geometrically but cuts bandwidth, so there is an optimum n for a required gain-bandwidth; in practice cascode or feedback is preferred to brute-force cascading.
• Miller effect in a CE/CS stage multiplies C_μ (or C_gd) by (1 + |Av|) at the input — the main bandwidth killer that the cascode removes.

Special two-transistor combinations

• Cascode (CE–CB or CS–CG): the CE stage drives a CB stage whose input resistance is only ≈ 1/gm, so the CE gain is ≈ −1 and Miller multiplication almost vanishes → very wide bandwidth. Output resistance is boosted: Ro ≈ gm2·ro2·(ro1‖r_π2) for BJT, ≈ gm2·ro1·ro2 for MOS, giving very high gain when loaded by a current source.
• Darlington (CC–CC): β ≈ β1β2 (exactly β1β2 + β1 + β2), very high input resistance, but V_BE(on) ≈ 1.4 V, leakage current multiplied, higher V_CE(sat), and slow because the first transistor's collector is not isolated. Used in power switching (TIP122) and relay drivers (ULN2003 array).
• CC–CE: emitter follower in front to raise input resistance without losing the CE gain.
• Current mirror / active load: a transistor acting as the load gives a very high small-signal resistance (ro) in a small area with a small DC drop — the standard way to get high gain in ICs.

The differential (emitter-coupled / long-tailed) pair

• Two matched transistors share a common emitter (or source) node fed by a tail current source I_EE (or I_SS); collector resistors R_C; inputs v1, v2.
• Definitions: differential input v_id = v1 − v2; common-mode input v_icm = (v1 + v2)/2. Output may be taken differentially (v_C1 − v_C2) or single-ended (one collector).
• DC bias: with v1 = v2, I_C1 = I_C2 ≈ I_EE/2, V_C1 = V_C2 = V_CC − (I_EE/2)R_C. The quiescent point is set by the tail source, not by R_C — a big advantage over single-ended biasing.
• Large-signal transfer characteristic (BJT): I_C1 = αI_EE/(1 + e^−v_id/V_T), I_C2 = αI_EE/(1 + e^+v_id/V_T), so I_C1 − I_C2 = αI_EE·tanh(v_id/2V_T). Linear within 1 % only for |v_id| ≲ 9 mV; essentially fully switched (≈96 %) by |v_id| ≈ 4V_T ≈ 100 mV at room temperature.
• MOS pair: i_D1,2 = (I_SS/2) ± (I_SS/V_OV)(v_id/2)√(1 − (v_id/2V_OV)²); full switching at v_id = √2·V_OV. The linear range is set by the overdrive V_OV, so MOS pairs handle larger differential swing than BJT pairs.
• Emitter degeneration: adding R_E in each emitter extends the linear range to roughly ±I_EE·R_E and reduces gain to R_C/(r_e + R_E) — the classic linearity-versus-gain trade.

Small-signal analysis: the half-circuit method

• Differential half circuit: apply +v_id/2 and −v_id/2. By symmetry the tail node is a virtual AC ground, so analyse one side as a plain CE stage.
  • Single-ended output: Ad = −gm R_C/2. Differential output: Ad = −gm R_C (with ro: −gm(R_C‖ro)).
  • Differential input resistance R_id = 2r_π (BJT) or ∞ (MOS, at DC).
• Common-mode half circuit: apply v_icm to both; the tail current splits, so each half sees an emitter resistance of 2R_EE.
  • Single-ended: Acm ≈ −R_C/(2R_EE + 1/gm) ≈ −R_C/(2R_EE). Differential output: Acm = 0 for a perfectly matched pair.
  • Common-mode input resistance per side ≈ r_π + (1 + β)·2R_EE — very large.
• CMRR = |Ad/Acm|; in dB, CMRR(dB) = 20 log₁₀|Ad/Acm|. For single-ended output CMRR ≈ gm·R_EE, so the tail resistance is everything: replacing R_EE by a current source (Ro of hundreds of kΩ to MΩ) raises CMRR by 30–40 dB.
• Active-load pair: a pnp/PMOS current mirror as load converts differential to single-ended without losing 6 dB and gives Ad ≈ gm(ro_n‖ro_p) — the 741/CMOS op-amp input stage.

Mismatch, offset and limits

• Input offset voltage V_OS: the differential input needed to make the output zero. Sources: ΔR_C/R_C → V_OS ≈ V_T(ΔR_C/R_C); ΔI_S/I_S → V_OS ≈ V_T(ΔI_S/I_S); for MOS, ΔV_t plus (V_OV/2)(Δ(W/L)/(W/L)).
• Input bias current I_B = (I_B1 + I_B2)/2 ≈ I_C/β; input offset current I_OS = |I_B1 − I_B2|. Drift with temperature: dV_OS/dT ≈ V_OS/T, so 1 mV of offset drifts ≈ 3.3 µV/°C at 300 K; the −2 mV/°C drift of V_BE itself is common-mode and cancels.
• Mismatch also sets finite CMRR: even with an ideal tail source, ΔR_C or Δgm converts common-mode input into differential output.
• Common-mode input range (ICMR) is bounded below by keeping the tail source in its active region and above by keeping the transistors out of saturation/triode.
• Slew and swing: the maximum current available to charge the following stage is only I_EE, which eventually limits slew rate in an op-amp built from this pair.
• Standards note: no Indian Standard prescribes amplifier topology; device and IC parameter definitions and test methods follow the IEC 60747 (discrete semiconductors) and IEC 60748 (integrated circuits) series adopted by BIS, and equipment-level EMC/safety is covered by the relevant IS/IEC product standards — check the current BIS catalogue, since the adopted editions are revised periodically.

Key points

• Cascading - overall gain is the product of stage gains, each computed with the next stage's input resistance as load.
• dB addition - 20 log₁₀ for voltage/current ratios, 10 log₁₀ for power ratios; stage gains in dB simply add.
• Stage ordering - CC/CD first for high Rin, CE/CS for gain, CC/CD last for low Rout.
• Bandwidth shrinkage - f_H* = f_H√(2^1/n − 1) and f_L* = f_L/√(2^1/n − 1) for n identical stages.
• Rise time - t_r ≈ 0.35/f_H; cascade t_r ≈ 1.1√(Σ t_ri²).
• RC coupling - no DC response, cheap; transformer - impedance matching, bulky; direct - DC response, drift.
• Cascode - CE–CB; kills the Miller effect, boosts Ro to ≈ gm·ro·ro, gives high gain with wide bandwidth.
• Darlington - β ≈ β1β2, V_BE ≈ 1.4 V, high Rin but slow and leaky.
• Differential pair - amplifies v1 − v2, rejects the common-mode part; the universal IC input stage.
• Tail current source - sets Q-point (I_C ≈ I_EE/2) and, through its high output resistance, sets CMRR.
• Half-circuit rule - differential drive makes the tail node an AC ground; common-mode drive makes each emitter see 2R_EE.
• Gains - Ad = −gm R_C (differential output) or −gm R_C/2 (single-ended); Acm ≈ −R_C/2R_EE single-ended.
• CMRR - ≈ gm·R_EE for single-ended output; 20 log₁₀ of the ratio in dB; limited by mismatch even with an ideal tail.
• R_id = 2r_π for BJT; differential input resistance of a MOS pair is essentially infinite at DC.
• Linear range - BJT pair linear only to about ±10 mV (tanh law); MOS pair to about ±V_OV/√2; emitter degeneration extends it.
• Active load - current-mirror load converts differential to single-ended with no 6 dB loss and gives Ad ≈ gm(ro_n‖ro_p).
• Offset - V_OS ≈ V_T(ΔR_C/R_C) or V_T(ΔI_S/I_S); I_OS = |I_B1 − I_B2|.
• Drift immunity - equal temperature drift in both halves is common-mode and is rejected; this is why direct coupling works in ICs.

Formulas and examples

Example 1 — two-stage RC-coupled amplifier with loading. Both stages CE, I_C = 1 mA, β = 100, V_T = 25 mV, R_C1 = R_C2 = 4.7 kΩ, R_L = 10 kΩ, biasing resistors large enough to neglect.

• gm = 1 mA/25 mV = 40 mA/V; r_π = 100/0.04 = 2.5 kΩ → R_in2 = 2.5 kΩ.
• Stage 1 load = 4.7 ‖ 2.5 = (4.7×2.5)/7.2 = 1.632 kΩ → Av1 = −0.04 × 1632 = −65.3.
• Stage 2 load = 4.7 ‖ 10 = 47/14.7 = 3.197 kΩ → Av2 = −0.04 × 3197 = −127.9.
• Overall Av = (−65.3)(−127.9) = +8,350 (non-inverting, two inversions) = 20 log₁₀(8350) = 78.4 dB.
• Note the cost of loading: unloaded, stage 1 would have given −188 instead of −65.3, i.e. 9.2 dB lost at that one interface.

Example 2 — bandwidth shrinkage and rise time. Three identical stages, each with f_L = 20 Hz, f_H = 1 MHz, gain 20 dB.

• Overall mid-band gain = 3 × 20 = 60 dB (×1000).
• √(2^1/3 − 1) = √(1.2599 − 1) = √0.2599 = 0.5098.
• f_H* = 1 MHz × 0.5098 = 509.8 kHz; f_L* = 20/0.5098 = 39.2 Hz. Bandwidth has halved.
• Rise times: t_r1 = 0.35/10⁶ = 0.35 µs each → t_r(total) ≈ 1.1√(3 × 0.35²) = 1.1 × 0.606 = 0.667 µs, which agrees with 0.35/509.8 kHz = 0.686 µs to about 3 %.

Example 3 — BJT differential pair, resistive tail versus current source. V_CC = 12 V, I_EE = 1 mA, R_C = 10 kΩ, R_EE = 100 kΩ, β = 150, V_T = 25 mV, ro neglected.

• DC: I_C1 = I_C2 = 0.5 mA → V_C1 = V_C2 = 12 − (0.5 mA)(10 kΩ) = 7 V.
• gm = 0.5/25 = 0.02 S; r_π = 150/0.02 = 7.5 kΩ → R_id = 15 kΩ.
• Ad (differential output) = −0.02 × 10,000 = −200; single-ended = −100.
• Acm (single-ended) = −10,000/(200,000 + 50) = −0.050.
• CMRR = 100/0.050 = 2000 = 66.0 dB (check: gm·R_EE = 0.02 × 100 kΩ = 2000 ✓).
• Replace R_EE by a current source of Ro = 2 MΩ: CMRR = 0.02 × 2×10⁶ = 40,000 = 92.0 dB — a 26 dB gain for one extra transistor pair, with no change in Ad.
• If v_id = 5 mV is applied differentially, differential output = 200 × 5 mV = 1 V; if a 1 V common-mode hum rides on both inputs, the single-ended output ripple is only 1 × 0.050 = 50 mV (and ideally zero differentially).

Example 4 — MOS differential pair, resistive and active load. I_SS = 400 µA, μnCox(W/L) = 1 mA/V², λ = 0.02 V⁻¹, R_D = 10 kΩ.

• I_D = 200 µA each; gm = √(2 × 1 mA/V² × 0.2 mA) = √(4×10⁻⁷) = 0.632 mA/V; V_OV = 2I_D/gm = 0.4 mA/0.632 mA/V = 0.633 V.
• Resistive load: Ad (differential) = −0.632 m × 10 k = −6.32 (16 dB) — modest, because gm of a MOSFET is small.
• Full switching at v_id = √2 × 0.633 = 0.895 V (versus ≈ 0.1 V for the BJT pair).
• Active (current-mirror) load: ro = 1/(λI_D) = 1/(0.02 × 200 µA) = 250 kΩ each → Ad = 0.632 m × (250 k ‖ 250 k = 125 k) = 79 (38 dB) from the same current — 22 dB more than the resistive version.

Example 5 — offset and linearity. Same pair as Example 3.

• 2 % mismatch in R_C: V_OS ≈ 25 mV × 0.02 = 0.5 mV, which appears at the output as 200 × 0.5 mV = 100 mV of DC error.
• I_B = 0.5 mA/150 = 3.33 µA per input; a 5 % β mismatch gives I_OS ≈ 0.17 µA.
• Adding R_E = 200 Ω per emitter: r_e = 1/gm = 50 Ω → Ad(diff) = −10,000/(50 + 200) = −40 (gain cut 5×), while the linear input range widens to roughly ±I_EE·R_E = ±(1 mA × 200 Ω) = ±200 mV.

Where it is used

• Op-amp and comparator ICs: the 741, LM324, OP-07, TL072 and every CMOS op-amp begin with a differential pair plus active load, followed by a gain stage and a buffer — designed and verified by analog teams at Texas Instruments India (Bengaluru), Analog Devices, NXP, ST and Cypress/Infineon India.
• Instrumentation and medical electronics: three-op-amp instrumentation amplifiers (AD620 class) for strain gauges, load cells, ECG/EEG front ends made by Indian firms such as BPL Medical and Skanray, where CMRR of 100 dB or more rejects 50 Hz mains pick-up on long leads.
• Industrial and process instrumentation: 4–20 mA transmitters, thermocouple and RTD inputs on PLC/DCS cards, weighbridge amplifiers — all rely on differential inputs to reject ground-loop and common-mode noise in plant wiring.
• VLSI and SoC design roles: differential pairs form comparators in SAR/flash ADCs, sense amplifiers in SRAM, input stages of LVDS/SerDes receivers, and the error amplifier in every SMPS controller — core interview material at Qualcomm, Intel, Samsung SRI-B, Cadence, Synopsys and Sankalp/eInfochips service companies.
• RF and communication receivers: the cascode LNA and the Gilbert-cell mixer (two cross-coupled differential pairs) in IF/RF strips used in defence and space electronics at BEL, DRDO labs, ISRO/SCL.
• Audio and power electronics: multistage RC- and transformer-coupled amplifiers, Darlington output pairs in audio and in relay/motor drivers (ULN2003, TIP122) across Indian industrial equipment.

Interview questions

• Q: Why is the overall gain of a cascade not simply the product of the open-circuit stage gains? A: Each stage is loaded by the input resistance of the next, so its effective load is R_C ‖ R_in(next); ignoring this overestimates the gain, sometimes by several times.
• Q: Why does bandwidth shrink when stages are cascaded? A: Each stage attenuates by its own roll-off, so the product falls 3 dB earlier; for n identical stages f_H* = f_H√(2^1/n − 1).
• Q: What makes the tail node an AC ground for differential signals? A: With +v_id/2 and −v_id/2 applied to a matched pair, the two emitter currents change equally and oppositely, so the net current into the tail node — and hence its voltage swing — is zero.
• Q: Does increasing R_C improve CMRR in a single-ended-output pair? A: No. Ad and Acm both scale with R_C, so CMRR ≈ gm·R_EE is unchanged; only a larger tail resistance (a current source) or a larger gm helps.
• Q: Why is a current source better than a resistor for the tail? A: It gives a very high small-signal resistance for CMRR without the large DC voltage drop and supply headroom a big resistor would need, and it sets the bias current precisely.
• Q: What does a current-mirror active load do for a differential pair? A: It converts the differential signal to single-ended without the 6 dB loss of taking one collector, and presents a very high resistance (ro) so the gain becomes gm(ro_n‖ro_p).
• Q: How large a differential input can a BJT pair handle linearly? A: Only about ±10 mV for 1 % linearity, because the transfer law is tanh(v_id/2V_T); emitter degeneration or a MOS pair with large V_OV extends this.
• Q: Why does a cascode have such a wide bandwidth? A: The common-base stage presents ≈ 1/gm to the driving CE stage, so that stage's gain is about −1 and the Miller multiplication of C_μ is only about 2 instead of (1 + |Av|).
• Q: Why is a Darlington pair slow? A: The first transistor's collector is tied to the supply side with no isolation, so it works into a large effective capacitance and never leaves the active region quickly; storage time and leakage are also multiplied.
• Q: Where does input offset voltage of a differential pair come from, and how is it trimmed? A: From mismatch in I_S, R_C or V_t; it is reduced by careful layout (common-centroid, large devices), laser/fuse trimming, or chopper and auto-zero techniques.
• Q: If both inputs of a differential amplifier are tied together and driven by 1 V, what appears at the differential output? A: Ideally zero; in practice a small output set by mismatch, which is what finite CMRR measures.
• Q: Why is direct coupling acceptable inside an IC but troublesome in discrete design? A: On a chip the devices are matched and at the same temperature, so drift is common-mode and is rejected by the differential structure; discrete transistors drift independently and the drift is amplified by every following stage.

Common mistakes

• Multiplying unloaded stage gains, or using r_π of the first stage as the load for itself instead of using the next stage's input resistance.
• Adding gains in dB and then multiplying again, or using 10 log₁₀ for a voltage ratio.
• Using Ad = −gm R_C for a single-ended output (it is −gm R_C/2) or dividing the differential-output gain by 2 as well — count the factor of ½ exactly once.
• Forgetting the 2R_EE in the common-mode half circuit, or putting R_EE instead of 2R_EE.
• Taking the quiescent collector current as I_EE instead of I_EE/2 when computing gm and the DC output level.
• Quoting CMRR as a plain ratio when the question asks for dB (or vice versa), and assuming an ideal tail source gives infinite CMRR — device mismatch still limits it.
• Applying small-signal results to inputs of tens of millivolts, where the pair is already in its non-linear tanh region and is behaving as a limiter.

Related topics

Amplifiers and feedback · BJT and MOSFET · FET amplifiers and biasing · Operational amplifiers · Active filters and op-amp applications · Oscillators and power supplies